Patents by Inventor Andrew J. Declercq

Andrew J. Declercq has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9274829
    Abstract: A mechanism is provided for handling interrupt actions for inter-thread communication. In association with a first processor thread, a thread action data structure is provided that comprises a non-blocking synchronization data structure and an internal list data structure of pending interrupts having no form of synchronization. A post of an interrupt action is received from a second processor thread to the thread action data structure associated with the first processor thread, where the interrupt action is added to the non-blocking synchronization data structure of the thread action data structure. The interrupt action is moved from the non-blocking synchronization data structure to the internal list data structure of pending interrupts for handling by the first processor thread. The internal list data structure of pending interrupts is processed to thereby handle interrupt actions moved to the internal list data structure.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: March 1, 2016
    Assignee: International Business Machines Corporation
    Inventors: Andrew J. Declercq, Ahmed Gheith, Aditya Kumar
  • Patent number: 9262331
    Abstract: A memory buffer with a set of one or more structures is created by a process of a first software program. The first memory buffer comprises a predetermined amount of memory. It is determined that a structure of the set of one or more structures has been or will be consumed by a second software program that supports the first software program. The consumption of the structure of the set of one or more structures indicates that memory associated with the structure of the set of one or more structures is being reclaimed. In response to the determination that the structure of the set of one or more structures has been or will be consumed, data is written from a first location to a second location. The first location is in memory allocated to the first software program and the second location is indicated for data storage.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Andrew J. Declercq, Ahmed Gheith, Andrew R. Malota
  • Patent number: 9262332
    Abstract: A memory buffer with a set of one or more structures is created by a process of a first software program. The first memory buffer comprises a predetermined amount of memory. It is determined that a structure of the set of one or more structures has been or will be consumed by a second software program that supports the first software program. The consumption of the structure of the set of one or more structures indicates that memory associated with the structure of the set of one or more structures is being reclaimed. In response to the determination that the structure of the set of one or more structures has been or will be consumed, data is written from a first location to a second location. The first location is in memory allocated to the first software program and the second location is indicated for data storage.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Andrew J. Declercq, Ahmed Gheith, Andrew R. Malota
  • Patent number: 9256461
    Abstract: A mechanism is provided for handling interrupt actions for inter-thread communication. In association with a first processor thread, a thread action data structure is provided that comprises a non-blocking synchronization data structure and an internal list data structure of pending interrupts having no form of synchronization. A post of an interrupt action is received from a second processor thread to the thread action data structure associated with the first processor thread, where the interrupt action is added to the non-blocking synchronization data structure of the thread action data structure. The interrupt action is moved from the non-blocking synchronization data structure to the internal list data structure of pending interrupts for handling by the first processor thread. The internal list data structure of pending interrupts is processed to thereby handle interrupt actions moved to the internal list data structure.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: February 9, 2016
    Assignee: International Business Machines Corporation
    Inventors: Andrew J. Declercq, Ahmed Gheith, Aditya Kumar
  • Publication number: 20150268988
    Abstract: A mechanism is provided for handling interrupt actions for inter-thread communication. In association with a first processor thread, a thread action data structure is provided that comprises a non-blocking synchronization data structure and an internal list data structure of pending interrupts having no form of synchronization. A post of an interrupt action is received from a second processor thread to the thread action data structure associated with the first processor thread, where the interrupt action is added to the non-blocking synchronization data structure of the thread action data structure. The interrupt action is moved from the non-blocking synchronization data structure to the internal list data structure of pending interrupts for handling by the first processor thread. The internal list data structure of pending interrupts is processed to thereby handle interrupt actions moved to the internal list data structure.
    Type: Application
    Filed: June 5, 2015
    Publication date: September 24, 2015
    Inventors: Andrew J. Declercq, Ahmed Gheith, Aditya Kumar
  • Publication number: 20150261684
    Abstract: A memory buffer with a set of one or more structures is created by a process of a first software program. The first memory buffer comprises a predetermined amount of memory. It is determined that a structure of the set of one or more structures has been or will be consumed by a second software program that supports the first software program. The consumption of the structure of the set of one or more structures indicates that memory associated with the structure of the set of one or more structures is being reclaimed. In response to the determination that the structure of the set of one or more structures has been or will be consumed, data is written from a first location to a second location. The first location is in memory allocated to the first software program and the second location is indicated for data storage.
    Type: Application
    Filed: May 29, 2015
    Publication date: September 17, 2015
    Inventors: Andrew J. Declercq, Ahmed Gheith, Andrew R. Malota
  • Publication number: 20150121029
    Abstract: A memory buffer with a set of one or more structures is created by a process of a first software program. The first memory buffer comprises a predetermined amount of memory. It is determined that a structure of the set of one or more structures has been or will be consumed by a second software program that supports the first software program. The consumption of the structure of the set of one or more structures indicates that memory associated with the structure of the set of one or more structures is being reclaimed. In response to the determination that the structure of the set of one or more structures has been or will be consumed, data is written from a first location to a second location. The first location is in memory allocated to the first software program and the second location is indicated for data storage.
    Type: Application
    Filed: October 24, 2013
    Publication date: April 30, 2015
    Applicant: International Business Machines Corporation
    Inventors: Andrew J. Declercq, Ahmed Gheith, Andrew R. Malota
  • Publication number: 20150082324
    Abstract: A mechanism is provided for handling interrupt actions for inter-thread communication. In association with a first processor thread, a thread action data structure is provided that comprises a non-blocking synchronization data structure and an internal list data structure of pending interrupts having no form of synchronization. A post of an interrupt action is received from a second processor thread to the thread action data structure associated with the first processor thread, where the interrupt action is added to the non-blocking synchronization data structure of the thread action data structure. The interrupt action is moved from the non-blocking synchronization data structure to the internal list data structure of pending interrupts for handling by the first processor thread. The internal list data structure of pending interrupts is processed to thereby handle interrupt actions moved to the internal list data structure.
    Type: Application
    Filed: September 18, 2013
    Publication date: March 19, 2015
    Applicant: International Business Machines Corporation
    Inventors: Andrew J. Declercq, Ahmed Gheith, Aditya Kumar
  • Patent number: 8539474
    Abstract: A method of organizing interim software fixes is disclosed. The method includes communicating with a user to understand a first software operation problem and determining if a first interim software fix to remedy the first software operation problem exists within an archive comprising a plurality of interim software fixes. In response to determining the first interim software fix exists, making available to the user an electronic package for installing the first interim software fix to remedy the first software operation problem. In response to determining the first interim software fix does not exist, causing to be developed the first interim software fix to remedy the first software operation problem. The method further includes creating an electronic package for the first interim software fix, making available to the user the electronic package for the first interim software fix and storing information associated with the first software operating problem in the archive.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: September 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Andrew J. Declercq, Cheryl L. Hall
  • Publication number: 20080098382
    Abstract: A method of organizing interim software fixes is disclosed. The method includes communicating with a user to understand a first software operation problem and determining if a first interim software fix to remedy the first software operation problem exists within an archive comprising a plurality of interim software fixes. In response to determining the first interim software fix exists, making available to the user an electronic package for installing the first interim software fix to remedy the first software operation problem. In response to determining the first interim software fix does not exist, causing to be developed the first interim software fix to remedy the first software operation problem. The method further includes creating an electronic package for the first interim software fix, making available to the user the electronic package for the first interim software fix and storing information associated with the first software operating problem in the archive.
    Type: Application
    Filed: September 28, 2006
    Publication date: April 24, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew J. Declercq, Cheryl L. Hall