Abstract: Circuits and methods for full rate data reception and transmission using half-frequency clock signals are disclosed. In one embodiment, a flop circuit includes a data input, a data output, and a clock input. The clock signal has a first frequency, while the flop circuit is configured to output data at a rate corresponding to a second frequency. In one embodiment, the second frequency is twice the first frequency. The flop circuit is configured to transmit a first data bit responsive to a first edge (e.g., a rising edge) of the clock signal and a second data bit responsive to a second edge (e.g., a falling edge) of the clock signal that is the next edge following the first edge. Accordingly, the flop circuit may effectively operate at the second frequency utilizing the clock signal at the first lower frequency.

Abstract: Circuits and methods for full rate data reception and transmission using half-frequency clock signals are disclosed. In one embodiment, a flop circuit includes a data input, a data output, and a clock input. The clock signal has a first frequency, while the flop circuit is configured to output data at a rate corresponding to a second frequency. In one embodiment, the second frequency is twice the first frequency. The flop circuit is configured to transmit a first data bit responsive to a first edge (e.g., a rising edge) of the clock signal and a second data bit responsive to a second edge (e.g., a falling edge) of the clock signal that is the next edge following the first edge. Accordingly, the flop circuit may effectively operate at the second frequency utilizing the clock signal at the first lower frequency.

Abstract: In one embodiment, a jitter detector comprises a logic circuit coupled to receive a plurality of inputs indicative of states captured from a plurality of outputs of a delay chain responsive to a first clock input and a plurality of clocked storage devices coupled to the logic circuit. The logic circuit is configured to identify a first input of the plurality of inputs that is: (i) captured in error from a corresponding one of the plurality of outputs of the delay chain, and (ii) the corresponding one of the plurality of outputs of the delay chain is least delayed by the delay chain among the plurality of outputs that are captured in error. The plurality of clocked storage devices are configured to accumulate an indication of which of the plurality of outputs have been captured in error over a plurality of clock cycles of the first clock input.

Abstract: In one embodiment, an integrated circuit includes at least one digital leakage detector that includes digital circuitry configured to detect an approximation of a magnitude of the leakage current in transistors of the integrated circuit and configured to generate a digital output representing the approximated magnitude. In another embodiment, a leak detector includes leak circuits and clocked storage devices. Each leak circuit is configured to generate an output signal indicative of a different magnitude of leakage current in a transistor. The clocked storage devices are configured to capture a state representing the output signals of the leak circuits. In another embodiment, a method includes running a test for leakage current in a digital leakage detector, wherein a digital output of the digital leakage detector represents a magnitude of a leakage current being experienced by the integrated circuit during use; and outputting the digital output from the integrated circuit.

Abstract: In one embodiment, a combined mux/storage circuit comprises a latch element, a plurality of passgates connected to the latch element, and logic circuitry. Each passgate has an input coupled to receive a signal representing a respective mux input and is configured to open and close responsive to respective pairs of control signals. The logic circuitry is coupled to receive a clock signal, a delayed clock signal, and mux select control signals, and is configured to generate pulses on the pair of control signals to control a passgate that has an input coupled to receive the signal representing a selected mux inputs, as indicated by the mux select control signals. The width of the pulses is dependent on the clock signal and the delayed clock signal. The latch element is configured to latch the signal representing the selected mux input in parallel with the selected mux input being driven as an output of the mux/storage circuit.

Abstract: An interconnect structure includes a signal wire and an active shield line adjacent to, but removed from, the signal wire. The interconnect structure also includes another active shield line adjacent to, but removed from, the signal wire. A signal driver is connected to the signal wire. The signal driver drives a pulse on the signal wire. A shield driver is connected to the active shield line. The shield driver asserts a signal on the active shield line substantially simultaneous with the pulse. Another shield driver is connected to the another active shield line. The another shield driver asserts a signal on the another active shield line substantially simultaneous with the pulse. The effect of the simultaneous signals on the signal wire and the active shield lines is to effectively cancel the lateral capacitances between these lines.

Abstract: An interconnect structure includes a signal wire and an active shield line adjacent to, but removed from, the signal wire. The interconnect structure also includes another active shield line adjacent to, but removed from, the signal wire. A signal driver is connected to the signal wire. The signal driver drives a pulse on the signal wire. A shield driver is connected to the active shield line. The shield driver asserts a signal on the active shield line substantially simultaneous with the pulse. Another shield driver is connected to the another active shield line. The another shield driver asserts a signal on the another active shield line substantially simultaneous with the pulse. The effect of the simultaneous signals on the signal wire and the active shield lines is to effectively cancel the lateral capacitances between these lines.