Patents by Inventor Andrew J. Mawer

Andrew J. Mawer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device having a ball grid array and method therefor
    Publication number: 20030102535
    Abstract: A semiconductor device (50) includes a semiconductor die (52) having electronic circuitry that is connected to a substrate (54). The substrate (54) is used to interface the semiconductor die (52) to a printed circuit board (64). The substrate (54) includes a plurality of bonding pads (56, 58). A first portion of the plurality of bonding pads are soldermask defined (SMD) bonding pads (56) and a second portion of the plurality of bonding pads are non-soldermask defined (NSMD) bonding pads (58). Using a combination of SMD and NSMD bonding pads provides the advantages of good thermal cycling reliability and good bending reliability over devices that have only SMD bonding pads or NSMD bonding pads.
    Type: Application
    Filed: January 15, 2003
    Publication date: June 5, 2003
    Inventors: Terry E. Burnette, Thomas H. Koschmieder, Andrew J. Mawer
  • Semiconductor device having a ball grid array and method therefor
    Patent number: 6552436
    Abstract: A semiconductor device (50) includes a semiconductor die (52) having electronic circuitry that is connected to a substrate (54). The substrate (54) is used to interface the semiconductor die (52) to a printed circuit board (64). The substrate (54) includes a plurality of bonding pads (56, 58). A first portion of the plurality of bonding pads are soldermask defined (SMD) bonding pads (56) and a second portion of the plurality of bonding pads are non-soldermask defined (NSMD) bonding pads (58). Using a combination of SMD and NSMD bonding pads provides the advantages of good thermal cycling reliability and good bending reliability over devices that have only SMD bonding pads or NSMD bonding pads.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: April 22, 2003
    Assignee: Motorola, Inc.
    Inventors: Terry E. Burnette, Thomas H. Koschmieder, Andrew J. Mawer
  • Semiconductor device having a ball grid array and method therefor
    Publication number: 20020070451
    Abstract: A semiconductor device (50) includes a semiconductor die (52) having electronic circuitry that is connected to a substrate (54). The substrate (54) is used to interface the semiconductor die (52) to a printed circuit board (64). The substrate (54) includes a plurality of bonding pads (56, 58). A first portion of the plurality of bonding pads are soldermask defined (SMD) bonding pads (56) and a second portion of the plurality of bonding pads are non-soldermask defined (NSMD) bonding pads (58). Using a combination of SMD and NSMD bonding pads provides the advantages of good thermal cycling reliability and good bending reliability over devices that have only SMD bonding pads or NSMD bonding pads.
    Type: Application
    Filed: December 8, 2000
    Publication date: June 13, 2002
    Inventors: Terry E. Burnette, Thomas H. Koschmieder, Andrew J. Mawer
  • Masking of circuit board vias to reduce heat-induced board and chip carrier package warp during wavesolder process
    Patent number: 5511306
    Abstract: A technique for minimizing heat-induced chipside solder joint fractures involving BGA (Ball Grid Array) components mounted on a multilayer printed circuit board when the board is passed through a wavesolder oven. The technique involves shielding the chipside solder joints from the effects of conductive heating by covering the through vias positioned underneath the BGA components with an insulating material. The insulating materials include silk screen material, solder mask and KAPTON tape. During wavesolder, the insulating material blocks conductive heat flow from the exposed board face through the vias and into the BGA component landing areas. With the wavesolder heat flow blocked, the BGA landing areas and BGA components experience much less heat deformation, and a much lower solder joint defect rate is achieved. Selection of silk screen, solder mask or KAPTON tape is based on a balance of solder process conditions and effective insulation capability, with the lowest cost, most effective solution preferred.
    Type: Grant
    Filed: April 5, 1994
    Date of Patent: April 30, 1996
    Assignee: Compaq Computer Corporation
    Inventors: Ronald D. Denton, George H. Bumgardner, Timothy M. McGuiggan, Andrew J. Mawer