Abstract: Apparatuses, systems, and techniques to process image frames. In at least one embodiment, one or more neural networks are used to blend two or more video frames between a first video frame and a second video frame. In at least one embodiment, a blended video frame is used to generate an intermediate video frame between the first video frame and the second video frame.

Abstract: Apparatuses, systems, and techniques to scale textured images using a Fourier transform in conjunction with one or more neural networks. In at least one embodiment, a neural network generates an expanded image from an input image by applying a Fourier transform to one or more feature maps generated by said neural network and up-scaling one or more resulting frequency domain feature maps before generating an expanded output image based on up-scaled feature maps.

Abstract: A method, computer readable medium, and system are disclosed for creating an image utilizing a map representing different classes of specific pixels within a scene. One or more computing systems use the map to create a preliminary image. This preliminary image is then compared to an original image that was used to create the map. A determination is made whether the preliminary image matches the original image, and results of the determination are used to adjust the computing systems that created the preliminary image, which improves a performance of such computing systems. The adjusted computing systems are then used to create images based on different input maps representing various object classes of specific pixels within a scene.

Abstract: A method, computer readable medium, and system are disclosed for creating an image utilizing a map representing different classes of specific pixels within a scene. One or more computing systems use the map to create a preliminary image. This preliminary image is then compared to an original image that was used to create the map. A determination is made whether the preliminary image matches the original image, and results of the determination are used to adjust the computing systems that created the preliminary image, which improves a performance of such computing systems. The adjusted computing systems are then used to create images based on different input maps representing various object classes of specific pixels within a scene.

Abstract: One embodiment of the present invention includes a memory management unit (MMU) that is configured to manage sparse mappings. The MMU processes requests to translate virtual addresses to physical addresses based on page table entries (PTEs) that indicate a sparse status. If the MMU determines that the PTE does not include a mapping from a virtual address to a physical address, then the MMU responds to the request based on the sparse status. If the sparse status is active, then the MMU determines the physical address based on whether the type of the request is a write operation and, subsequently, generates an acknowledgement of the request. By contrast, if the sparse status is not active, then the MMU generates a page fault. Advantageously, the disclosed embodiments enable the computer system to manage sparse mappings without incurring the performance degradation associated with both page faults and conventional software-based sparse mapping management.

Abstract: A system and method for tracking and reporting texture map levels of detail that are computed during graphics processing allows for efficient management of texture map storage. Minimum and/or maximum pre-clamped texture map levels of detail values are tracked by a graphics processor and an array stored in memory is updated to report the minimum and/or maximum values for use by an application program. The minimum and/or maximum values may be used to determine the active set of texture map levels of detail that is loaded into graphics memory.

Abstract: One embodiment of the present invention includes a memory management unit (MMU) that is configured to manage sparse mappings. The MMU processes requests to translate virtual addresses to physical addresses based on page table entries (PTEs) that indicate a sparse status. If the MMU determines that the PTE does not include a mapping from a virtual address to a physical address, then the MMU responds to the request based on the sparse status. If the sparse status is active, then the MMU determines the physical address based on whether the type of the request is a write operation and, subsequently, generates an acknowledgement of the request. By contrast, if the sparse status is not active, then the MMU generates a page fault. Advantageously, the disclosed embodiments enable the computer system to manage sparse mappings without incurring the performance degradation associated with both page faults and conventional software-based sparse mapping management.

Abstract: An apparatus and method for buffering graphics data are described. In one embodiment, a graphics processing apparatus includes a storage unit and a reorder control unit that is connected to the storage unit. The reorder control unit is configured to coordinate storage of vertex attributes in the storage unit so as to convert the vertex attributes from an initial order to a modified order. The reorder control unit is configured to identify a subset of the vertex attributes to be stored within a common range of addresses in the storage unit, and the reorder control unit is configured to access the storage unit such that the subset of the vertex attributes is written into the storage unit substantially in parallel.

Abstract: A system, method and computer program product are provided for packing graphics attributes. In use, a plurality of graphics attributes is identified. Such graphics attributes are packed, such that the packed graphics attributes are capable of being processed utilizing a pixel shader.

Abstract: The invention sets forth an approach to context switching that utilizes scan chains modified to perform context switching operations. The design requires substantially less additional silicon area and design engineering effort than existing context switch approaches, while operating substantially faster and providing additional debug observability during context switching operations.

Abstract: An apparatus and method for buffering graphics data are described. In one embodiment, a graphics processing apparatus includes a memory and a buffering unit that is connected to the memory. The buffering unit is configured to buffer vertex attributes en route to the memory. The buffering unit is configured to coalesce a subset of the vertex attributes to be stored within a common range of addresses in the memory, and the buffering unit is configured to issue a single write request to the memory on behalf of the subset of the vertex attributes.

Abstract: An apparatus and method for converting color data from one color space to another color space. A driver determines that a set of shader program instructions perform a color conversion function and the set of shader program instructions are replaced with either a single shader program instruction or a flag is set within an existing shader program instruction to specify that output color data is represented in a nonlinear color format. The output color data is converted to the nonlinear color format prior to being stored in a frame buffer. Nonlinear color data read from the frame buffer is converted to a linear color format prior to shading, blending, or raster operations.

Abstract: An output buffer in a multi-threaded processor is managed to store a variable amount of output data. Parallel threads produce a variable amount of output data. A controller is configured to determine how much output buffer space is needed per thread and how many threads can execute in parallel, given the available space in the output buffer. The controller also determines where each thread writes to in the output buffer.

Abstract: Apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a graphics processing apparatus includes a clipping engine and an output unit connected to the clipping engine. The clipping engine is configured to clip an input graphics primitive with respect to a set of clipping planes to derive spatial attributes of new vertices. The output unit is configured to identify a subset of the new vertices that defines an output graphics primitive, and the output unit is configured to derive non-spatial attributes of the subset of the new vertices to produce the output graphics primitive.

Abstract: Apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a clipping module includes a clipping engine and a clipping controller connected to the clipping engine. The clipping controller is configured to determine which edges of an input graphics primitive intersect a first clipping plane. The clipping controller is configured to direct the clipping engine to clip, with respect to the first clipping plane, a first pair of edges of the input graphics primitive in response to determining that the first pair of edges intersect the first clipping plane.

Abstract: An apparatus and method for converting color data from one color space to another color space. A driver determines that a set of shader program instructions perform a color conversion function and the set of shader program instructions are replaced with either a single shader program instruction or a flag is set within an existing shader program instruction to specify that output color data is represented in a nonlinear color format. The output color data is converted to the nonlinear color format prior to being stored in a frame buffer. Nonlinear color data read from the frame buffer is converted to a linear color format prior to shading, blending, or raster operations.

Abstract: An apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a graphics processing apparatus includes a clipping unit, a read-only memory that is connected to the clipping unit, a read-write memory that is connected to the clipping unit, and an addressing unit that is connected to the read-only memory and the read-write memory. The read-only memory is configured to store a clipping program, and the read-write memory is configured to store a patch program. The addressing unit is configured to selectively address one of the read-only memory and the read-write memory based on a set of input conditions.

Abstract: Vertices defining a graphics primitive are converted into homogeneous space and clipped against a single clipping plane, the w=0 plane, to produce a clipped graphics primitive having vertices including w coordinates that are greater than or equal to zero. Rasterizing a graphics primitive having a vertex with a w coordinates that is greater than or equal to zero is less complex than rasterizing a graphics primitive having a vertex with a w coordinate that is less than zero. Clipping against the w=0 plane is less complex than conventional clipping since conventional clipping may require that the graphics primitive be clipped against each of the six faces of the viewing frustum to produce a clipped graphics primitive.

Abstract: Apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a graphics processing apparatus includes a mapping unit and a clipping engine that is connected to the mapping unit. The mapping unit is configured to map a graphics primitive onto a canonical representation. The clipping engine is configured to perform a set of clipping operations with respect to the canonical representation.

Abstract: A content addressable memory with an internally-timed write operation includes a data input for receiving a input word. Coupled to the data input are a plurality of storage registers comprising stored words. Each storage register includes a comparison circuit for comparing the stored word with the input word and producing therefrom a match output indicating a match when the stored word matches the input word, and indicating a miss when the stored word does not match the input word. Coupled to the storage registers is a miss detector for generating a miss signal responsive to each of the match outputs of the storage registers indicating a miss. Coupled to the miss detector is a write cycle circuit for writing the input word to at least one of the storage registers responsive to receiving the miss signal.