Abstract: Methods for optimizing an initial placement a number of features over a clock signal distribution network on an integrated circuit (IC), wherein the plurality of features includes a plurality of registers and a corresponding plurality of local drivers are presented, the methods including: characterizing the number of features by a number of register groupings, the number of register groupings defined by similarity of corresponding local drivers, wherein each of the number of register groupings is physically delimited by a defined region on the clock signal distribution network in the initial placement; and iteratively moving the number of register groupings in accordance with a number of exception based rules over an increasingly widening area of comparison to create an optimized placement of the number of features.