Abstract: A computer memory controller for interfacing to a host computer comprises a buffer memory for interfacing to a plurality of memory units and for holding data read thereto and therefrom. A central controller is operative to control the transfer of data to and from the host computer and the memory units. The buffer memory is controlled to form a plurality of buffer segments for addressably storing data read from or written to the memory units. The central controller is operative to allocate a buffer segment for a read or write request from the host computer, of a size sufficient for the data. The central controller is also operative in response to data requests from the host computer to control the memory units to seek a plurality of requested data stored in different memory units simultaneously.