Patents by Inventor Andrew James Read

Andrew James Read has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SINGLE-CHIP INTEGRATED CIRCUIT WITH CAPACITIVE ISOLATION AND METHOD FOR MAKING THE SAME
    Publication number: 20160163692
    Abstract: An integrated circuit, including at least two integrated circuit portions mutually spaced on a single electrically insulating die and at least one coupling region on the die to provide capacitive coupling between the otherwise mutually isolated integrated circuit portions, the integrated circuit portions being formed by a plurality of layers on the single die, the layers including metal and dielectric layers and at least one semiconductor layer; wherein at least one of the dielectric layers extends from the integrated circuit portions across the coupling region and at least a corresponding one of the metal layers and/or at least one semiconductor layer extends from each of the integrated circuit portions and partially across the coupling region to form capacitors therein and thereby provide the capacitive coupling between the integrated circuit portions.
    Type: Application
    Filed: February 17, 2016
    Publication date: June 9, 2016
    Inventors: Yashodhan Vijay Moghe, Andrew Terry, Andrew James Read, Steven Grant Duvall
  • Single-chip integrated circuit with capacitive isolation and method for making the same
    Patent number: 9299655
    Abstract: An integrated circuit, including at least two integrated circuit portions mutually spaced on a single electrically insulating die and at least one coupling region on the die to provide capacitive coupling between the otherwise mutually isolated integrated circuit portions, the integrated circuit portions being formed by a plurality of layers on the single die, the layers including metal and dielectric layers and at least one semiconductor layer; wherein at least one of the dielectric layers extends from the integrated circuit portions across the coupling region and at least a corresponding one of the metal layers and/or at least one semiconductor layer extends from each of the integrated circuit portions and partially across the coupling region to form capacitors therein and thereby provide the capacitive coupling between the integrated circuit portions.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: March 29, 2016
    Assignee: THE SILANNA GROUP PTY LTD
    Inventors: Yashodhan Vijay Moghe, Andrew Terry, Andrew James Read, Steven Grant Duvall
  • SINGLE-CHIP INTEGRATED CIRCUIT WITH CAPACITIVE ISOLATION
    Publication number: 20140145301
    Abstract: An integrated circuit, including at least two integrated circuit portions mutually spaced on a single electrically insulating die and at least one coupling region on the die to provide capacitive coupling between the otherwise mutually isolated integrated circuit portions, the integrated circuit portions being formed by a plurality of layers on the single die, the layers including metal and dielectric layers and at least one semiconductor layer; wherein at least one of the dielectric layers extends from the integrated circuit portions across the coupling region and at least a corresponding one of the metal layers and/or at least one semiconductor layer extends from each of the integrated circuit portions and partially across the coupling region to form capacitors therein and thereby provide the capacitive coupling between the integrated circuit portions.
    Type: Application
    Filed: November 18, 2011
    Publication date: May 29, 2014
    Applicant: THE SILANNA GROUP PTY LTD
    Inventors: Yashodhan Vijay Moghe, Andrew Terry, Andrew James Read, Steven Grant Duvall