Patents by Inventor Andrew John Sowden
Andrew John Sowden has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7940546Abstract: A ROM array is provided, comprising a plurality of columns of memory cells, wherein each column of memory cells is coupled to a shared bit line which is shared by that column of memory cells and an adjacent column of memory cells. Each column of memory cells has its own associated reference line, which is selectively coupled to a reference potential. Each reference line is coupled to the reference potential when a read operation is performed on a memory cell of the associated column of memory cells. Each reference line is decoupled from the reference potential when a read operation is performed on a memory cell of the adjacent column of memory cells. Both reference lines associated, via their columns of memory cells, to a shared bit line are decoupled from the reference potential when the shared bit line is being pre-charged prior to the read operation. The present invention thus provides a ROM array in which both leakage reduction and speed increase benefits result, whilst providing a high density design.Type: GrantFiled: January 30, 2009Date of Patent: May 10, 2011Assignee: ARM LimitedInventors: Sriram Thyagarajan, Gus Yeung, Andrew John Sowden
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Publication number: 20100195365Abstract: A ROM array is provided, comprising a plurality of columns of memory cells, wherein each column of memory cells is coupled to a shared bit line which is shared by that column of memory cells and an adjacent column of memory cells. Each column of memory cells has its own associated reference line, which is selectively coupled to a reference potential. Each reference line is coupled to the reference potential when a read operation is performed on a memory cell of the associated column of memory cells. Each reference line is decoupled from the reference potential when a read operation is performed on a memory cell of the adjacent column of memory cells. Both reference lines associated, via their columns of memory cells, to a shared bit line are decoupled from the reference potential when the shared bit line is being pre-charged prior to the read operation. The present invention thus provides a ROM array in which both leakage reduction and speed increase benefits result, whilst providing a high density design.Type: ApplicationFiled: January 30, 2009Publication date: August 5, 2010Applicant: ARM LIMITEDInventors: Sriram Thyagarajan, Gus Yeung, Andrew John Sowden
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Patent number: 7723867Abstract: A control device for controlling power supplied to circuitry is disclosed. The circuitry comprises a plurality of portions, each of said plurality of circuit portions being arranged between a first voltage level source and a second voltage level source, said first and second voltage level sources being adapted to output different voltage levels; said control device being adapted to control power supplied to each of said plurality of circuit portions.Type: GrantFiled: May 30, 2007Date of Patent: May 25, 2010Assignee: ARM LimitedInventors: David John Willingham, Andrew John Sowden
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Patent number: 7696649Abstract: The power control circuitry comprises a series of power switching circuits, each power switching circuit being associated with one of the circuit portions and being provided with an enable signal and responsive to its enable signal being set to connect the voltage source to the at least one voltage line of the associated circuit portion. Further, at least one enable qualifying circuit is provided, each such enable qualifying circuit being associated with one of the power switching circuits and being arranged to generate an output signal used to determine the enable signal provided to a later power switching circuit in the series. Each enable qualifying circuit sets its output signal when both the enable signal provided to the associated power switching circuit is set and the at least one voltage line of the circuit portion associated with that power switching circuit has reached a predetermined voltage level.Type: GrantFiled: August 13, 2007Date of Patent: April 13, 2010Assignee: ARM LimitedInventors: Christophe Frey, Andrew John Sowden
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Patent number: 7558104Abstract: An array of storage elements each comprising a data input and output and a feedback loop, substantially all of said feedback loops being formed with an asymmetry such that on power up when no input data signal is received a value is preferentially stored in said feedback loops such that substantially all of said storage elements will preferentially output a same value.Type: GrantFiled: February 5, 2007Date of Patent: July 7, 2009Assignee: ARM LimitedInventors: Andrew John Sowden, David Anthony New, Paul Darren Hoxey, Simon Christopher Reynolds
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Publication number: 20090045677Abstract: A power control circuitry and method of operation are provided for controlling the connection of a voltage source to an associated circuit when that circuit is to enter an active state of operation. The associated circuit has a plurality of circuit portions, and each circuit portion has at least one voltage line for connection to the voltage source. The power control circuitry comprises a series of power switching circuits, each power switching circuit being associated with one of the circuit portions and being provided with an enable signal. Each power switching circuit is responsive to its enable signal being set to connect the voltage source to the at least one voltage line of the associated circuit portion. Further, at least one enable qualifying circuit is provided, each such enable qualifying circuit being associated with one of the power switching circuits and being arranged to generate an output signal used to determine the enable signal provided to a later power switching circuit in the series.Type: ApplicationFiled: August 13, 2007Publication date: February 19, 2009Applicant: ARM LimitedInventors: Christophe Frey, Andrew John Sowden
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Publication number: 20080297063Abstract: A control device for controlling power supplied to circuitry is disclosed. The circuitry comprises a plurality of portions, each of said plurality of circuit portions being arranged between a first voltage level source and a second voltage level source, said first and second voltage level sources being adapted to output different voltage levels; said control device being adapted to control power supplied to each of said plurality of circuit portions.Type: ApplicationFiled: May 30, 2007Publication date: December 4, 2008Inventors: David John Willingham, Andrew John Sowden
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Publication number: 20080189483Abstract: An array of storage elements each comprising a data input and output and a feedback loop, substantially all of said feedback loops being formed with an asymmetry such that on power up when no input data signal is received a value is preferentially stored in said feedback loops such that substantially all of said storage elements will preferentially output a same value.Type: ApplicationFiled: February 5, 2007Publication date: August 7, 2008Applicant: ARM LimitedInventors: Andrew John Sowden, David Anthony New, Paul Darren Hoxey, Simon Christopher Reynolds
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Patent number: 7005889Abstract: A data processing apparatus and method are provided for controlling level shifting. The data processing apparatus comprises a first component provided within a first voltage domain and operable to receive a first supply voltage, and a second component provided within a second voltage domain and operable to receive a second supply voltage. At least one of the first and second supply voltages are dynamically variable. The data processing apparatus further comprises an interface cell between the first and second voltage domains which is operable to receive a signal issued by the first component in the first voltage domain and destined for the second component. The interface cell comprises level shifting logic operable to convert the signal issued by the first component into a corresponding signal to be propagated to the second component in the second voltage domain.Type: GrantFiled: July 9, 2004Date of Patent: February 28, 2006Assignee: ARM LimitedInventors: Andrew John Sowden, Dipesh Ishwerbhai Patel, Nicholas Andrew Salter, Harry Edward Oldham