Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a channel structure extending between a first source/drain region and a second source/drain region. Further, a gate electrode is arranged directly over the channel structures, and an upper interconnect contact is arranged over and coupled to the gate electrode. A backside contact is arranged below and coupled to the first source/drain region. The backside contact has a width that decreases from a bottommost surface of the backside contact to a topmost surface of the backside contact.

Abstract: A method of semiconductor fabrication includes positioning a substrate on a susceptor in a chamber and growing an epitaxial feature on the substrate. The growing includes providing UV radiation to a first region of a surface of the substrate and while providing the UV radiation, growing a first portion of the epitaxial feature on the first region of the surface while concurrently growing a second portion of the epitaxial feature on a second region of the surface of the substrate. The first portion of the epitaxial feature can be greater in thickness than the second portion of the epitaxial feature.

Abstract: A method for filling a gap in a semiconductor structure includes: forming the gap between two raised portions of the semiconductor structure, the gap having a bottom surface and two lateral surfaces each extending upwardly from the bottom surface along one of the raised portions to terminate at an upper surface of a corresponding one of the raised portions; and forming a filler element in the gap in a bottom-up manner that avoids the filler element being formed laterally.

Abstract: A method includes: applying a first solution to a semiconductor structure of a semiconductor device to form a first coating, the semiconductor structure including a feature and the trench, the first coating being formed in the trench and over the feature, the first solution containing a metal-containing solute; heating the first coating in a multi-step procedure to turn the first coating into a first film, the multi-step procedure including heating at a first temperature, followed by heating at a second temperature not lower than the first temperature; applying a second solution onto the first film to form a second coating, the second solution containing the metal-containing solute; and heating the second coating in a multi-step procedure to turn the second coating into a second film, the multi-step procedure including heating at a third temperature, followed by heating at a fourth temperature not lower than the third temperature.

Abstract: A semiconductor device includes first and second semiconductor fins, a first gate structure, and a second gate structure. The first and second semiconductor fins respectively includes a first channel region and a second channel region, which the first and second gate structures are respectively on. The first gate structure includes a first silicon oxide layer on the first channel region, a first high-k dielectric layer on the first silicon oxide layer, and a first metal gate on the first high-k dielectric layer. The second gate structure includes a second silicon oxide layer on the second channel region, a second high-k dielectric layer on the second silicon oxide layer, and a second metal gate on the second high-k dielectric layer. The first silicon oxide layer has a Si4+ ion concentration greater than a Si4+ ion concentration of a bottom portion of the second silicon oxide layer.

Abstract: A semiconductor device includes first and second semiconductor fins, a first gate structure, and a second gate structure. The first and second semiconductor fins respectively includes a first channel region and a second channel region, which the first and second gate structures are respectively on. The first gate structure includes a first silicon oxide layer on the first channel region, a first high-k dielectric layer on the first silicon oxide layer, and a first metal gate on the first high-k dielectric layer. The second gate structure includes a second silicon oxide layer on the second channel region, a second high-k dielectric layer on the second silicon oxide layer, and a second metal gate on the second high-k dielectric layer. The first silicon oxide layer has a Si4+ ion concentration greater than a Si4+ ion concentration of a bottom portion of the second silicon oxide layer.

Abstract: Methods for manufacturing semiconductor structures are provided. The method for manufacturing the semiconductor structure includes forming a fin structure protruding from a substrate and forming a source/drain structure over the fin structure. The method for manufacturing a semiconductor structure further includes forming a metallic layer over the source/drain structure and forming an oxide film on a sidewall of the source/drain structure. In addition, the oxide film and the metallic layer are both in direct contact with the source/drain structure.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a channel structure extending between a first source/drain region and a second source/drain region. Further, a gate electrode is arranged directly over the channel structures, and an upper interconnect contact is arranged over and coupled to the gate electrode. A backside contact is arranged below and coupled to the first source/drain region. The backside contact has a width that decreases from a bottommost surface of the backside contact to a topmost surface of the backside contact.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a channel structure extending between a first source/drain region and a second source/drain region. Further, a gate electrode is arranged directly over the channel structures, and an upper interconnect contact is arranged over and coupled to the gate electrode. A backside contact is arranged below and coupled to the first source/drain region. The backside contact has a width that decreases from a bottommost surface of the backside contact to a topmost surface of the backside contact.

Abstract: A method of semiconductor fabrication includes positioning a substrate on a susceptor in a chamber and growing an epitaxial feature on the substrate. The growing includes providing UV radiation to a first region of a surface of the substrate and while providing the UV radiation, growing a first portion of the epitaxial feature on the first region of the surface while concurrently growing a second portion of the epitaxial feature on a second region of the surface of the substrate. The first portion of the epitaxial feature can be greater in thickness than the second portion of the epitaxial feature.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a channel structure extending between a first source/drain region and a second source/drain region. Further, a gate electrode is arranged directly over the channel structures, and an upper interconnect contact is arranged over and coupled to the gate electrode. A backside contact is arranged below and coupled to the first source/drain region. The backside contact has a width that decreases from a bottommost surface of the backside contact to a topmost surface of the backside contact.

Abstract: A method of semiconductor fabrication includes positioning a substrate on a susceptor in a chamber and growing an epitaxial feature on the substrate. The growing includes providing UV radiation to a first region of a surface of the substrate and while providing the UV radiation, growing a first portion of the epitaxial feature on the first region of the surface while concurrently growing a second portion of the epitaxial feature on a second region of the surface of the substrate. The first portion of the epitaxial feature can be greater in thickness than the second portion of the epitaxial feature.

Abstract: The present disclosure provides an integrated circuit with an interconnect structure and a method for forming the integrated circuit. In one embodiment, a method of the present disclosure includes receiving a workpiece that includes a first recess in a dielectric layer over the workpiece, depositing a contact fill in the first recess and over the dielectric layer to form a contact feature, planarizing a top surface of the workpiece to remove the contact fill over the dielectric layer, depositing an interlayer dielectric layer over the planarized top surface of the workpiece, forming a second recess in the interlayer dielectric layer to expose the contact fill in the dielectric layer, recessing the contact fill by soaking the workpiece in a room temperature ionic liquid, and depositing a conductive layer over the recessed contact fill. The material forming the contact fill is soluble in the room temperature ionic liquid.

Abstract: A method includes depositing a plurality of first semiconductor layers and a plurality of second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers are stacked alternately; patterning the first and second semiconductor layers to form a fin structure; supplying a first bias to the substrate after patterning the first and second semiconductor layers; and etching the second semiconductor layers when the semiconductor substrate is supplied with the first bias, wherein etching the second semiconductor layers is performed such that the first semiconductor layers are suspended above the substrate.

Abstract: Methods for manufacturing semiconductor structures are provided. The method for manufacturing the semiconductor structure includes forming a fin structure protruding from a substrate and forming a source/drain structure over the fin structure. The method for manufacturing a semiconductor structure further includes forming a metallic layer over the source/drain structure and forming an oxide film on a sidewall of the source/drain structure. In addition, the oxide film and the metallic layer are both in direct contact with the source/drain structure.

Abstract: A semiconductor device includes first and second semiconductor fins, a first gate structure, and a second gate structure. The first and second semiconductor fins respectively includes a first channel region and a second channel region, which the first and second gate structures are respectively on. The first gate structure includes a first silicon oxide layer on the first channel region, a first high-k dielectric layer on the first silicon oxide layer, and a first metal gate on the first high-k dielectric layer. The second gate structure includes a second silicon oxide layer on the second channel region, a second high-k dielectric layer on the second silicon oxide layer, and a second metal gate on the second high-k dielectric layer. The first silicon oxide layer has a Si4+ ion concentration greater than a Si4+ ion concentration of a bottom portion of the second silicon oxide layer.

Abstract: Methods for manufacturing semiconductor structures are provided. The method for manufacturing a semiconductor structure includes forming a source/drain structure over a substrate and forming a metal layer over the source/drain structure. The method for manufacturing a semiconductor structure further includes reacting a portion of the metal layer with the source/drain structure to form a metallic layer by using an etching solvent. In addition, the etching solvent includes (a) a first component and (b) a second component. The first component includes an acid, and the second component includes propylene carbonate (PC), ethylene carbonate (EC), diethyl carbonate (DEC), or a combination thereof.

Abstract: A method includes depositing a plurality of first semiconductor layers and a plurality of second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers are stacked alternately; patterning the first and second semiconductor layers to form a fin structure; supplying a first bias to the substrate after patterning the first and second semiconductor layers; and etching the second semiconductor layers when the semiconductor substrate is supplied with the first bias, wherein etching the second semiconductor layers is performed such that the first semiconductor layers are suspended above the substrate.

Abstract: A method of fabricating a semiconductor device includes forming a semiconductor fin comprising a channel region for a fin field effect transistor (finFET). A gate oxide layer is then formed on the channel. The gate oxide layer is treated with a nitrogen containing agent so as to form a nitrogenous layer and an interfacial layer. The nitrogenous layer is then removed. A high-k dielectric layer is formed on the interfacial layer. A metal gate is formed on the high-k dielectric layer. The nitrogenous layer is removed by rinsing the semiconductor fin with deionized water. The gate oxide and interfacial layer contains the same material.

Abstract: A FinFET device includes a substrate, a fin, and isolation regions on either side of the fin. The device also includes sidewall spacers above the isolation regions and formed along the fin structure. A recessing trench is formed by the sidewall spacers and the fin, and an epitaxially-grown semiconductor material is formed in and above the recessing trench, forming an epitaxial structure.