Patents by Inventor Andrew Joy
Andrew Joy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9530160Abstract: Various affinity systems and methods are provided to enable the capture of unique end-to-end purchase information. In some embodiments, the data collected through affinity systems and methods can be used to develop insights into the purchase making decision processes of users at any point of a shopping experience. The systems can host interaction platforms to facilitate the exchange of information, opinion, and/or suggestions on products, recommendations, and/or opinions. Further embodiments provide analysis of the captured data to derive insights regarding the appeal of products/services and the qualitative opinions of the users about the products/services.Type: GrantFiled: March 13, 2014Date of Patent: December 27, 2016Assignee: Nanigans, Inc.Inventors: Andrew Man-Hon Lau, Joseph Taisup Chung, David Andrew Joy, Kwan Hong Lee, Aatish Dilip Salvi
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Publication number: 20140279233Abstract: Provided in some embodiments is a social platform for soliciting qualified opinions and facilitating shopping, engaging shoppers, and delivering feedback. The social platform can communicate or integrate with existing sites to provide options for interacting with other qualified users. The platform can improve engagement, and increase social interaction. In some embodiments, affinity/feedback systems are provided that generate feedback for shoppers during their shopping experience. In addition to providing real-time feedback and opinions to shoppers, affinity and feedback systems can be configured to analyze and stored information on a complete purchasing experience. The complete purchasing experience can include, for example, initial identification of interest (e.g.Type: ApplicationFiled: March 13, 2014Publication date: September 18, 2014Inventors: Andrew Man-Hon Lau, Joseph Taisup Chung, David Andrew Joy, Kwan Hong Lee, Aatish Dilip Salvi
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Publication number: 20140279232Abstract: Various affinity systems and methods are provided to enable the capture of unique end-to-end purchase intent information. In some embodiments, the data collected through affinity systems and methods can be used to develop insights into the purchase making decision processes of users at any point of a shopping experience. The systems can host interaction platforms to facilitate the exchange of information, opinion, and/or suggestions on products, recommendations, and/or opinions. Further embodiments provide analysis of the captured data to derive insights regarding the appeal of products/services and the qualitative opinions of the users about the products/services.Type: ApplicationFiled: March 13, 2014Publication date: September 18, 2014Inventors: Andrew Man-Hon Lau, Joseph Taisup Chung, David Andrew Joy, Kwan Hong Lee, Aatish Dilip Salvi
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Publication number: 20140279130Abstract: Various affinity systems and methods are provided to enable the capture of unique end-to-end purchase information. In some embodiments, the data collected through affinity systems and methods can be used to develop insights into the purchase making decision processes of users at any point of a shopping experience. The systems can host interaction platforms to facilitate the exchange of information, opinion, and/or suggestions on products, recommendations, and/or opinions. Further embodiments provide analysis of the captured data to derive insights regarding the appeal of products/services and the qualitative opinions of the users about the products/services.Type: ApplicationFiled: March 13, 2014Publication date: September 18, 2014Inventors: Andrew Man-Hon Lau, Joseph Taisup Chung, David Andrew Joy, Kwan Hong Lee, Aatish Dilip Salvi
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Patent number: 8619934Abstract: A clock data recovery system is described. It includes a high pass filter for transmitting a filtered data signal in response to receiving an input data signal; an adder for summing the filtered data signal with a feedback signal, wherein the adder produces a summed input signal; a plurality of clocked data comparators for receiving the summed input signal, wherein the clocked data comparators determine an input data bit value; a plurality of clocked error comparators for receiving an error signal associated with clock recovery; an equalization and adaptation logic for selecting an error sample such that a phase associated with the error sample is locked at a second post cursor; and a phase mixer for transmitting a delay in response to receiving the phase and the delay is transmitted to the clocked-data comparators and the clocked-error comparators.Type: GrantFiled: August 11, 2010Date of Patent: December 31, 2013Assignee: Texas Instruments IncorporatedInventors: Hae-Chang Lee, Arnold Robert Feldman, Andrew Joy
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Publication number: 20110041008Abstract: A clock data recovery system is described. It includes a high pass filter for transmitting a filtered data signal in response to receiving an input data signal; an adder for summing the filtered data signal with a feedback signal, wherein the adder produces a summed input signal; a plurality of clocked data comparators for receiving the summed input signal, wherein the clocked data comparators determine an input data bit value; a plurality of clocked error comparators for receiving an error signal associated with clock recovery; an equalization and adaptation logic for selecting an error sample such that a phase associated with the error sample is locked at a second post cursor; and a phase mixer for transmitting a delay in response to receiving the phase and the delay is transmitted to the clocked-data comparators and the clocked-error comparators.Type: ApplicationFiled: August 11, 2010Publication date: February 17, 2011Inventors: Hae-Chang Lee, Arnold Robert Feldman, Andrew Joy
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Patent number: 7519484Abstract: There is provided a power supply monitor circuit comprising a positive supply monitoring input, a negative supply monitoring input, and a voltage divider connected between the positive and negative supply monitoring inputs and having an intermediate node providing a potential intermediate those on the positive and negative supply monitoring inputs. A sampling circuit is connected to sample the potential at each of the positive supply input the negative supply input and the intermediate node. Also provided is a method of monitoring noise on a power supply whereby phase information from those samples is derived about the noise signals at the two said points.Type: GrantFiled: June 13, 2005Date of Patent: April 14, 2009Assignee: Texas Instruments IncorporatedInventors: Derek Colman, Andrew Joy, Tom Leslie
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Patent number: 7236556Abstract: In an integrated circuit receiving multiple serial data streams in parallel, a local clock is generated from each data stream and is synchronized with the data stream. Sometimes a data stream may have no transitions making it difficult to keep the clock synchronized with its data. A clock channel is provided, which always has edges. A circuit is provided for each data stream which measures the time elapsed since the data stream had an edge. After a certain period, the phase of the local clock is nudged towards that of the clock channel. Thereafter, the longer there are no edges on the data stream the more frequently nudges towards the phase of the clock channel are made.Type: GrantFiled: July 22, 2003Date of Patent: June 26, 2007Assignee: Texas Instruments IncorporatedInventors: Richard Ward, Giuseppe Surace, Andrew Joy
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Patent number: 7233628Abstract: A circuit for receiving multiple serial datastreams in parallel is disclosed. A bit clock is recovered from each data stream, there being one data bit for each transition of the clock signal both positive and negative going. The phases of the bit clocks are compared and are adjusted by 180 degrees so that the positive going edges of all occur close to each other. The bits of each stream are assembled into words under the control of a word clock. In one embodiment a common word clock is derived form the set of bit clocks as a whole. In another embodiment each stream is provided with its own word clock which is aligned to positive edges of the respective bit clocks that are close to each other.Type: GrantFiled: July 22, 2003Date of Patent: June 19, 2007Assignee: Texas Instruments IncorporatedInventors: Iain Robertson, Richard Simpson, Michael Harwood, Richard Ward, Andrew Joy, Robert Simpson
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Patent number: 7170962Abstract: A circuit for receiving multiple serial datastreams in parallel is disclosed. A bit clock is recovered from each data stream, there being one data bit for each transition of the clock signal both positive and negative going. The phases of the bit clocks are compared and are adjusted by 180 degrees so that the positive going edges of all occur close to each other. The bits of each stream are assembled into words under the control of a word clock. In one embodiment a common word clock is derived form the set of bit clocks as a whole. In another embodiment each stream is provided with its own word clock which is aligned to positive edges of the respective bit clocks that are close to each other.Type: GrantFiled: July 22, 2003Date of Patent: January 30, 2007Assignee: Texas Instruments IncorporatedInventors: Andrew Joy, Robert Simpson, Richard Ward
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Patent number: 7027522Abstract: A differential data transmission system that transmits encoded data symbols as differential signals. A signal for transmitting symbols on a set of at least three parallel channels, each channel having a first terminal, P1 to PN, and each channel having a second terminal connected to a common node Z. The signal comprising for each symbol an active signal on two of those channels and an inactive signal on the remaining channel or channels, the symbols being distinguishable by which two of the channels have the active signals.Type: GrantFiled: July 25, 2001Date of Patent: April 11, 2006Assignee: Texas Instruments IncorporatedInventors: Andrew Pickering, Sue Simpson, Andrew Joy
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Publication number: 20060036379Abstract: There is provided a power supply monitor circuit comprising a positive supply monitoring input, a negative supply monitoring input, and a voltage divider connected between the positive and negative supply monitoring inputs and having an intermediate node providing a potential intermediate those on the positive and negative supply monitoring inputs. A sampling circuit is connected to sample the potential at each of the positive supply input the negative supply input and the intermediate node. Also provided is a method of monitoring noise on a power supply whereby phase information from those samples is derived about the noise signals at the two said points.Type: ApplicationFiled: June 13, 2005Publication date: February 16, 2006Inventors: Derek Colman, Andrew Joy, Tom Leslie
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Publication number: 20050053171Abstract: A differential data transmission system that transmits encoded data symbols as differential signals. A signal for transmitting symbols on a set of at least three parallel channels, each channel having a first terminal, P1 to PN, and each channel having a second terminal connected to a common node Z. The signal comprising for each symbol an active signal on two of those channels and an inactive signal on the remaining channel or channels, the symbols being distinguishable by which two of the channels have the active signals.Type: ApplicationFiled: October 22, 2004Publication date: March 10, 2005Inventors: Andrew Pickering, Sue Simpson, Andrew Joy
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Publication number: 20040135602Abstract: In an integrated circuit receiving multiple serial data streams in parallel, a local clock is generated from each data stream and is synchronised with the data stream. Sometimes a data stream may have no transitions making it difficult to keep the clock synchronised with its data. A clock channel is provided, which always has edges. A circuit is provided for each data stream which measures the time elapsed since the data stream had an edge. After a certain period, the phase of the local clock is nudged towards that of the clock channel. Thereafter, the longer there are no edges on the data stream the more frequently nudges towards the phase of the clock channel are made.Type: ApplicationFiled: July 22, 2003Publication date: July 15, 2004Inventors: Richard Ward, Giuseppe Surace, Andrew Joy
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Publication number: 20040136484Abstract: A circuit for receiving multiple serial datastreams in parallel is disclosed. A bit clock is recovered from each data stream, there being one data bit for each transition of the clock signal both positive and negative going. The phases of the bit clocks are compared and are adjusted by 180 degrees so that the positive going edges of all occur close to each other. The bits of each stream are assembled into words under the control of a word clock. In one embodiment a common word clock is derived form the set of bit clocks as a whole. In another embodiment each stream is provided with its own word clock which is aligned to positive edges of the respective bit clocks that are close to each other.Type: ApplicationFiled: July 22, 2003Publication date: July 15, 2004Inventors: Andrew Joy, Robert Simpson, Richard Ward
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Publication number: 20020061072Abstract: A differential data transmission system that transmits encoded data symbols as differential signals. A signal for transmitting symbols on a set of at least three parallel channels, each channel having a first terminal, P1 to PN, and each channel having a second terminal connected to a common node Z. The signal comprising for each symbol an active signal on two of those channels and an inactive signal on the remaining channel or channels, the symbols being distinguishable by which two of the channels have the active signals.Type: ApplicationFiled: July 25, 2001Publication date: May 23, 2002Inventors: Andrew Pickering, Sue Simpson, Andrew Joy