Abstract: A teletext decoder includes a data acquisition and control circuit (DAC) which may be operated in either of two modes under the control of a microcontroller (MC). In one mode a framing code window used for detecting a framing code in received data pulses (D) is generated internally and is used in conjunction with data lines of a received video signal where teletext data is expected to occur. In the other mode a framing code window is generated externally by means of an applied line sync signal (S) and is used in conjunction with lines of a received video signal where teletext data is not expected to occur e.g. during ITS lines and normal picture lines. In this way the problem of "junk" data is greatly alleviated.

Abstract: A teletext decoder comprises a main memory (M2) which includes a raw data buffer (RDB) in rows RD0 to RDn of which teletext data packets and non-teletext "junk" data packets are stored in the order in which they are received, and a reformatting buffer (RB) to rows R0 to R31 of which the data packets stored in the RDB memory are transferred, the data packets in the RB memory being stored in a given numeral sequence. Each of the rows R0 to R31 of the buffer (RB) has a status buffer (SB) byte B0 to B31 respectively, associated with it for indicating whether the corresponding data packet has been received out of its correct given numerical sequence, and thereby being a possible non-teletext "junk" data packet which may be subsequently overwritten by a valid data packet.

Abstract: As shown in FIG. 2, a teletext decoder has a multi-page memory (MEM) comprising a plurality of memory portions (CH0 to CH3) in which individual pages can be stored on a priority basis. The numbers of selected pages are entered into page request registers (PR0 to PR3) and when the number of a selected page is detected by the relevent one of page comparators (PC0 to PC3) a found bit (FB) is produced by the relevant one of flip-flops (FB0 to FB3) and recorded in the memory portion allotted to the selected page by processor means (PM). In order to ensure that the end of a selected page can also be detected, one of the memory portions is allotted to store every page received so that a found bit is always produced at the end of a selected page stored in another memory portion. The processor means (PM) uses this latter found bit to signify detection of the end of the selected page.

Abstract: An improved arrangement for digital signal encrytion using a cipher algorithm in which a multi-bit key signal is used to produce a first keystream signal of coding bytes which are used in an exclusive-OR logical operation with data bytes of a received digital data signal to produce an enciphered/deciphered output digital data signal. Hitherto, the keysteam signal was also fed back into the algorithm for processing with the key signal, but this was found to result in an insecure arrangement because the keystream signal can be found by exclusive-ORing the received digital data signal with only a few bytes of the output data signal that are already known, following which the key signal itself can be deduced by a fairly simple trial-and-error computing procedure. The improvement consists in feeding back into the algorithm a keystream signal which is not the same as that used for the exclusive-OR logical operation.