Patents by Inventor Andrew Ka Lab Chan

Andrew Ka Lab Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8044682
    Abstract: An in-FPGA carry chain is provided that does not exhibit significant leakage current. In particular, parts of the carry chain can be switched on/off when desired. In this manner, carry chain parts can have their leakage currents substantially disabled when they are not in use, thus saving power. Additionally, there is provided a carry chain whose logic is separate from the other parts (e.g., LUTs) of the logic blocks that perform the remaining arithmetic functions, and whose inputs are the input data to be added, rather than data that is output in delayed fashion from the other parts (e.g., LUTs) of the logic blocks. Such a configuration reduces latency by allowing the carry chain to operate directly on the received input data without need to wait on results from the other parts (e.g., LUTs) of the logic blocks.
    Type: Grant
    Filed: June 1, 2009
    Date of Patent: October 25, 2011
    Assignee: Siliconblue Technologies Corporation
    Inventors: John Birkner, Andrew Ka Lab Chan
  • Patent number: 7911229
    Abstract: Parasitic static leakage current through input terminals of bus-accessing multiplexers is minimized by automatically forcing as many as practical of the bus lines into a high impedance state where all drivers of the lines are in a high impedance output state. Thus parasitic current sinking or current sourcing leakage paths through the bus-accessing multiplexers are cut off. The method is of particular utility in a low power FPGA that desirable has low static current leakage when in a static state.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: March 22, 2011
    Assignee: Siliconblue Technologies Corporation
    Inventor: Andrew Ka Lab Chan
  • Publication number: 20100301898
    Abstract: FPGA carry chain that does not exhibit significant leakage current. In particular, the carry chain can be switched on/off when desired. In this manner, carry chains can have their leakage currents substantially disabled when they are not in use, thus saving power. Additionally, a carry chain whose logic is separate from the logic blocks that perform the remaining arithmetic functions, and whose inputs are the input data to be added, rather than data from the logic blocks. Such a configuration reduces latency by allowing the carry chain to operate directly on the input data without need to wait on results from the logic blocks.
    Type: Application
    Filed: June 1, 2009
    Publication date: December 2, 2010
    Inventors: John Birkner, Andrew Ka Lab Chan
  • Publication number: 20100079166
    Abstract: Parasitic static leakage current through input terminals of bus-accessing multiplexers is minimized by automatically forcing as many as practical of the bus lines into a high impedance state where all drivers of the lines are in a high impedance output state. Thus parasitic current sinking or current sourcing leakage paths through the bus-accessing multiplexers are cut off. The method is of particular utility in a low power FPGA that desirable has low static current leakage when in a static state.
    Type: Application
    Filed: September 26, 2008
    Publication date: April 1, 2010
    Inventor: Andrew Ka Lab CHAN
  • Patent number: RE45200
    Abstract: Parasitic static leakage current through input terminals of bus-accessing multiplexers is minimized by automatically forcing as many as practical of the bus lines into a high impedance state where all drivers of the lines are in a high impedance output state. Thus parasitic current sinking or current sourcing leakage paths through the bus-accessing multiplexers are cut off. The method is of particular utility in a low power FPGA that desirable has low static current leakage when in a static state.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: October 21, 2014
    Assignee: Lattice Semiconductor Corporation
    Inventor: Andrew Ka Lab Chan