Abstract: A method for automatically creating a global routing solution for an integrated circuit. The method includes generating n original population of GR solutions. In one or more subsequent phases the method generates succeeding populations of GR solutions. The generation of each succeeding population includes determining a plurality of base GR solutions from the current population of GR solutions, determining a plurality of DRC hotspot areas within the plurality of base GR solutions, determining a plurality of patching GR solutions from which patches may be extracted, and hybridizing patching of GR solutions into base GR solutions.

Abstract: A method and system for designing an optimized specification of an integrated circuit (IC) is provided. The IC comprises a plurality of cells, and each of the cells comprises a plurality of transistors. The method includes preparing a linewidth map of at least one device of the plurality of devices, performing a topography-aware analysis of the at least one device based on the linewidth map, and designing the optimized specification of the IC based on the topography-aware analysis. In another embodiment, a method for estimating a leakage power of at least one device in an IC is provided. The method includes determining a defocus and a pitch value, determining a linewidth value based on the defocus and pitch value, and estimating the leakage current and/or leakage power based on the linewidth value.

Abstract: The present invention provides a method and system for designing an integrated circuit (IC). The IC comprises a plurality of cells, and each of the cells comprises a plurality of transistors. The method achieves a target objective of a transistor, of a cell, or of part of or the entire IC. The method of designing the IC includes reshaping a basic shape of the transistor. The method includes determining a reshaping bias solution of the transistor. The method further includes modifying the basic shape of the transistor channel, based on the reshaping bias solution, and preparing a reshaped layout design.

Abstract: A method and system for integrated circuit optimization to improve performance and to reduce leakage power consumption of an integrated circuit (IC). The original IC includes a plurality of nominal cells, and each of the nominal cells includes a plurality of transistors. The method creates an optimized standard-cell library from a standard-cell library. The standard-cell library includes a plurality of nominal cells, and each of the nominal cells includes a plurality of transistors. Further, an optimized IC is generated by using the optimized standard-cell library from the original IC. The optimized IC has an improved performance and reduced leakage power characteristics, as compared to the original IC.

Abstract: Method and apparatus for designing an integrated circuit. A new layout is generated for at least one standard cell that incorporates an auxiliary pattern on a gate layer to facilitate cell-based optical proximity correction. An original placement solution is modified for a plurality of standard cells to permit incorporation of cells containing auxiliary patterns while improving an objective function of a resulting placement solution for the plurality of standard cells.

Abstract: A method and system for detailed placement of layout objects in a standard-cell layout design are disclosed. Layout objects comprise cells and etch dummies. The method includes a programming based technique to calculate layout object perturbation distances for the layout objects. The method includes adjusting the layout objects with their corresponding layout object perturbation distances. This leads to improved photolithographic characteristics such as reduced Critical Dimension (CD) errors and forbidden pitches in the standard-cell layout.

Abstract: A method for performing a mask design layout resolution enhancement includes determining a level of correction for the design layout for a predetermined parametric yield with a minimum total correction cost. The design layout is corrected at the determined level of correction based on a correction algorithm if the correction is required. In this manner, only those printed features on the design layout that are critical for obtaining the desired performance yield are corrected, thereby reducing the total cost of correction of the design layout.

Abstract: A method and system for representing metal wires in Very Large Scale Integration (VLSI) circuit design in a simplified form. A pair of metal wires is considered at a time. A plurality of Piece Wise Linear (PWL) equations is created to represent sides each of the pair of metal wires. The plurality of PWL equations is used to determine an equivalent coupling capacitance of the pair of metal wires. The pair of metal wires is reshaped to form a pair of reshaped metal wires that are electrically equivalent.

Abstract: Systems of the invention employ peer-to-peer and centralized server networking to enable POTS/PSTN/PBX phone lines to be shared with other users of the system over the Internet. An example application of the invention is to allow a person, having access to an Internet connection, to receive calls and make calls using his/her home or office telephone, or using the phones of other parties that he/she is authorized to access. In preferred embodiments, the invention can exploit availability of an existing voice modem port on the user's home or office computer, and can require only the installation of software on the home or office computer, and on whatever device (laptop, PDA, computer, mobile phones, etc.) is employed by the user in the remote location.

Abstract: The present invention provides a method and system for improving reticle enhancement calculations during manufacture of an integrated circuit (IC). The reticle enhancement calculations are improved by incorporating post-planarization topography estimates. A planarization process of a wafer layer is simulated to estimate the post-planarization topography. RET calculations, such as sub-resolution assist feature insertion, optical proximity corrections and phase shifting are then performed based on the post-planarization topography of the wafer layer.