Abstract: According to an embodiment of the present invention, a capacitor comprising field effect transistors and a bias transistor.

Abstract: A digital-to-analog converter containing one or more ideal stages, a reduced-radix stage coupled with the one or more ideal stages, and a digital calibration logic section to operate on a calibration value. The calibration value is the difference between a first calibration constant and a second calibration constant. Digital input codes are received through the digital logic section. The calibration value is added to digital input codes with values that exceed the value of the second calibration constant. The outputs of the digital logic section are input to all stages of the digital-to-analog converter.

Abstract: A reference buffer circuit having a first reference voltage circuit to provide a first reference voltage at a first port to sink a first current at the first port; a second reference voltage circuit to provide a second reference voltage at a second port to sink a second current at the second port; and a current source circuit to source a source current at an output port, where the output port is connected to the second port. In one application, the first and second ports are connected to a resistor ladder network of a flash analog-to-digital converter.