Patents by Inventor Andrew Ketterson

Andrew Ketterson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11699629
    Abstract: The disclosure is directed to an integrated circuit (IC) die stacked with a backer die, including capacitors and thermal vias. The backer die includes a substrate material to contain and electrically insulate one or more capacitors at a back of the IC die. The backer die further includes a thermal material that is more thermally conductive than the substrate material for thermal spreading and increased heat dissipation. In particular, the backer die electrically couples capacitors to the IC die in a stacked configuration while also spreading and dissipating heat from the IC die. Such a configuration reduces an overall footprint of the electronic device, resulting in decreased integrated circuits (IC) packages and module sizes. In other words, instead of placing the capacitors next to the IC die, the capacitors are stacked on top of the IC die, thereby reducing an overall surface area of the package.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: July 11, 2023
    Assignee: Qorvo US, Inc.
    Inventors: Anthony Chiu, Bror Peterson, Andrew Ketterson
  • Publication number: 20220310471
    Abstract: The disclosure is directed to an integrated circuit (IC) die stacked with a backer die, including capacitors and thermal vias. The backer die includes a substrate material to contain and electrically insulate one or more capacitors at a back of the IC die. The backer die further includes a thermal material that is more thermally conductive than the substrate material for thermal spreading and increased heat dissipation. In particular, the backer die electrically couples capacitors to the IC die in a stacked configuration while also spreading and dissipating heat from the IC die. Such a configuration reduces an overall footprint of the electronic device, resulting in decreased integrated circuits (IC) packages and module sizes. In other words, instead of placing the capacitors next to the IC die, the capacitors are stacked on top of the IC die, thereby reducing an overall surface area of the package.
    Type: Application
    Filed: March 26, 2021
    Publication date: September 29, 2022
    Inventors: Anthony Chiu, Bror Peterson, Andrew Ketterson
  • Patent number: 10832984
    Abstract: A method includes the steps of fabricating one or more semiconductor devices on a semiconductor wafer and depositing one or more conformal organic environmental protection layers over the semiconductor wafer using a vapor deposition process. By depositing the one or more conformal organic environmental protection layers using a vapor deposition process, thin film conformal organic environmental protection layers may be provided that offer excellent protection against water and oxygen ingress, thus increasing the ruggedness and reliability of the resulting semiconductor die.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: November 10, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Christo Bojkov, Andrew Ketterson, Robert Charles Dry
  • Publication number: 20200152533
    Abstract: A method includes the steps of fabricating one or more semiconductor devices on a semiconductor wafer and depositing one or more conformal organic environmental protection layers over the semiconductor wafer using a vapor deposition process. By depositing the one or more conformal organic environmental protection layers using a vapor deposition process, thin film conformal organic environmental protection layers may be provided that offer excellent protection against water and oxygen ingress, thus increasing the ruggedness and reliability of the resulting semiconductor die.
    Type: Application
    Filed: January 15, 2020
    Publication date: May 14, 2020
    Inventors: Christo Bojkov, Andrew Ketterson, Robert Charles Dry
  • Patent number: 10651103
    Abstract: A method includes the steps of fabricating one or more semiconductor devices on a semiconductor wafer and depositing one or more conformal organic environmental protection layers over the semiconductor wafer using a vapor deposition process. By depositing the one or more conformal organic environmental protection layers using a vapor deposition process, thin film conformal organic environmental protection layers may be provided that offer excellent protection against water and oxygen ingress, thus increasing the ruggedness and reliability of the resulting semiconductor die.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: May 12, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Christo Bojkov, Andrew Ketterson, Robert Charles Dry
  • Patent number: 10615091
    Abstract: A method includes the steps of fabricating one or more semiconductor devices on a semiconductor wafer and depositing one or more conformal organic environmental protection layers over the semiconductor wafer using a vapor deposition process. By depositing the one or more conformal organic environmental protection layers using a vapor deposition process, thin film conformal organic environmental protection layers may be provided that offer excellent protection against water and oxygen ingress, thus increasing the ruggedness and reliability of the resulting semiconductor die.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: April 7, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Christo Bojkov, Andrew Ketterson, Robert Charles Dry
  • Publication number: 20180122716
    Abstract: A method includes the steps of fabricating one or more semiconductor devices on a semiconductor wafer and depositing one or more conformal organic environmental protection layers over the semiconductor wafer using a vapor deposition process. By depositing the one or more conformal organic environmental protection layers using a vapor deposition process, thin film conformal organic environmental protection layers may be provided that offer excellent protection against water and oxygen ingress, thus increasing the ruggedness and reliability of the resulting semiconductor die.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 3, 2018
    Inventors: Christo Bojkov, Andrew Ketterson, Robert Charles Dry
  • Patent number: 9472633
    Abstract: Embodiments include but are not limited to apparatuses and systems including a microelectronic device including a gate, a source pad and a drain pad arranged such that the gate is separated from the source pad and the drain pad by air, and an insulating layer coupled with a portion of the gate such that at least a portion of the insulating layer is separated from the source pad and the drain pad by the air. Methods for making the same also are described.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: October 18, 2016
    Assignee: Qorvo US, Inc.
    Inventors: Michael Schuette, Andrew Ketterson
  • Publication number: 20050012030
    Abstract: A photodetector includes a high-indium-concentration (H-I-C) absorption layer having a Group III sublattice indium concentration greater than 53%. The H-I-C absorption layer improves responsivity without decreasing bandwidth. The photoconversion structure that includes the H-I-C absorption layer can be formed on any type of substrate through the use of a metamorphic buffer layer to provide a lattice constant gradient between the photoconversion structure and the substrate. The responsivity of the photodetector can be further improved by passing an incoming optical signal through the H-I-C absorption layer at least twice.
    Type: Application
    Filed: July 16, 2003
    Publication date: January 20, 2005
    Inventors: Aaditya Mahajan, Edward Beam, Jose Jiminez, Andrew Ketterson