Patents by Inventor Andrew Ketterson
Andrew Ketterson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11699629Abstract: The disclosure is directed to an integrated circuit (IC) die stacked with a backer die, including capacitors and thermal vias. The backer die includes a substrate material to contain and electrically insulate one or more capacitors at a back of the IC die. The backer die further includes a thermal material that is more thermally conductive than the substrate material for thermal spreading and increased heat dissipation. In particular, the backer die electrically couples capacitors to the IC die in a stacked configuration while also spreading and dissipating heat from the IC die. Such a configuration reduces an overall footprint of the electronic device, resulting in decreased integrated circuits (IC) packages and module sizes. In other words, instead of placing the capacitors next to the IC die, the capacitors are stacked on top of the IC die, thereby reducing an overall surface area of the package.Type: GrantFiled: March 26, 2021Date of Patent: July 11, 2023Assignee: Qorvo US, Inc.Inventors: Anthony Chiu, Bror Peterson, Andrew Ketterson
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Publication number: 20220310471Abstract: The disclosure is directed to an integrated circuit (IC) die stacked with a backer die, including capacitors and thermal vias. The backer die includes a substrate material to contain and electrically insulate one or more capacitors at a back of the IC die. The backer die further includes a thermal material that is more thermally conductive than the substrate material for thermal spreading and increased heat dissipation. In particular, the backer die electrically couples capacitors to the IC die in a stacked configuration while also spreading and dissipating heat from the IC die. Such a configuration reduces an overall footprint of the electronic device, resulting in decreased integrated circuits (IC) packages and module sizes. In other words, instead of placing the capacitors next to the IC die, the capacitors are stacked on top of the IC die, thereby reducing an overall surface area of the package.Type: ApplicationFiled: March 26, 2021Publication date: September 29, 2022Inventors: Anthony Chiu, Bror Peterson, Andrew Ketterson
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Patent number: 10832984Abstract: A method includes the steps of fabricating one or more semiconductor devices on a semiconductor wafer and depositing one or more conformal organic environmental protection layers over the semiconductor wafer using a vapor deposition process. By depositing the one or more conformal organic environmental protection layers using a vapor deposition process, thin film conformal organic environmental protection layers may be provided that offer excellent protection against water and oxygen ingress, thus increasing the ruggedness and reliability of the resulting semiconductor die.Type: GrantFiled: January 15, 2020Date of Patent: November 10, 2020Assignee: Qorvo US, Inc.Inventors: Christo Bojkov, Andrew Ketterson, Robert Charles Dry
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Publication number: 20200152533Abstract: A method includes the steps of fabricating one or more semiconductor devices on a semiconductor wafer and depositing one or more conformal organic environmental protection layers over the semiconductor wafer using a vapor deposition process. By depositing the one or more conformal organic environmental protection layers using a vapor deposition process, thin film conformal organic environmental protection layers may be provided that offer excellent protection against water and oxygen ingress, thus increasing the ruggedness and reliability of the resulting semiconductor die.Type: ApplicationFiled: January 15, 2020Publication date: May 14, 2020Inventors: Christo Bojkov, Andrew Ketterson, Robert Charles Dry
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Patent number: 10651103Abstract: A method includes the steps of fabricating one or more semiconductor devices on a semiconductor wafer and depositing one or more conformal organic environmental protection layers over the semiconductor wafer using a vapor deposition process. By depositing the one or more conformal organic environmental protection layers using a vapor deposition process, thin film conformal organic environmental protection layers may be provided that offer excellent protection against water and oxygen ingress, thus increasing the ruggedness and reliability of the resulting semiconductor die.Type: GrantFiled: October 30, 2017Date of Patent: May 12, 2020Assignee: Qorvo US, Inc.Inventors: Christo Bojkov, Andrew Ketterson, Robert Charles Dry
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Patent number: 10615091Abstract: A method includes the steps of fabricating one or more semiconductor devices on a semiconductor wafer and depositing one or more conformal organic environmental protection layers over the semiconductor wafer using a vapor deposition process. By depositing the one or more conformal organic environmental protection layers using a vapor deposition process, thin film conformal organic environmental protection layers may be provided that offer excellent protection against water and oxygen ingress, thus increasing the ruggedness and reliability of the resulting semiconductor die.Type: GrantFiled: October 30, 2017Date of Patent: April 7, 2020Assignee: Qorvo US, Inc.Inventors: Christo Bojkov, Andrew Ketterson, Robert Charles Dry
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Publication number: 20180122716Abstract: A method includes the steps of fabricating one or more semiconductor devices on a semiconductor wafer and depositing one or more conformal organic environmental protection layers over the semiconductor wafer using a vapor deposition process. By depositing the one or more conformal organic environmental protection layers using a vapor deposition process, thin film conformal organic environmental protection layers may be provided that offer excellent protection against water and oxygen ingress, thus increasing the ruggedness and reliability of the resulting semiconductor die.Type: ApplicationFiled: October 30, 2017Publication date: May 3, 2018Inventors: Christo Bojkov, Andrew Ketterson, Robert Charles Dry
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Patent number: 9472633Abstract: Embodiments include but are not limited to apparatuses and systems including a microelectronic device including a gate, a source pad and a drain pad arranged such that the gate is separated from the source pad and the drain pad by air, and an insulating layer coupled with a portion of the gate such that at least a portion of the insulating layer is separated from the source pad and the drain pad by the air. Methods for making the same also are described.Type: GrantFiled: November 28, 2011Date of Patent: October 18, 2016Assignee: Qorvo US, Inc.Inventors: Michael Schuette, Andrew Ketterson
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Publication number: 20130320349Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device may include a buffer layer disposed on a substrate, the buffer layer including gallium (Ga) and nitrogen (N), a barrier layer disposed on the buffer layer, the barrier layer including aluminum (Al) and nitrogen (N), wherein the barrier layer includes an oxidized portion of the barrier layer, a gate dielectric disposed on the oxidized portion of the barrier layer, and a gate electrode disposed on the gate dielectric, wherein the oxidized portion of the barrier layer is disposed in a gate region between the gate electrode and the buffer layer.Type: ApplicationFiled: May 30, 2012Publication date: December 5, 2013Applicant: TRIQUINT SEMICONDUCTOR, INC.Inventors: Paul Saunier, Andrew A. Ketterson
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Patent number: 7148463Abstract: A photodetector includes a high-indium-concentration (H-I-C) absorption layer having a Group III sublattice indium concentration greater than 53%. The H-I-C absorption layer improves responsivity without decreasing bandwidth. The photoconversion structure that includes the H-I-C absorption layer can be formed on any type of substrate through the use of a metamorphic buffer layer to provide a lattice constant gradient between the photoconversion structure and the substrate. The responsivity of the photodetector can be further improved by passing an incoming optical signal through the H-I-C absorption layer at least twice.Type: GrantFiled: July 16, 2003Date of Patent: December 12, 2006Assignee: TriQuint Semiconductor, Inc.Inventors: Aaditya Mahajan, Edward A. Beam, III, Jose L. Jiminez, Andrew A. Ketterson
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Patent number: 7130124Abstract: A pitch averaging Bragg grating includes a plurality of grating peaks spaced by different pitch values. By selecting the different pitch values to have an average pitch value equal to a target pitch value, the pitch averaging Bragg grating can be made to perform like a constant pitch Bragg grating having a fixed pitch at the target pitch value. The different pitch values can be multiples of the minimum placement resolution of a production tool to be used to produce the Bragg grating. The pitch averaging Bragg grating can be used in place of constant pitch Bragg gratings in optical devices and systems, such as DFB lasers, DBR lasers, optical spectral filters, multi-wavelength laser arrays, and WDM systems.Type: GrantFiled: April 30, 2003Date of Patent: October 31, 2006Assignee: Tri Quint Semiconductor, Inc.Inventors: Andrew A. Ketterson, Jose L. Jimenez, Christopher T. Youtsey
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Publication number: 20050012030Abstract: A photodetector includes a high-indium-concentration (H-I-C) absorption layer having a Group III sublattice indium concentration greater than 53%. The H-I-C absorption layer improves responsivity without decreasing bandwidth. The photoconversion structure that includes the H-I-C absorption layer can be formed on any type of substrate through the use of a metamorphic buffer layer to provide a lattice constant gradient between the photoconversion structure and the substrate. The responsivity of the photodetector can be further improved by passing an incoming optical signal through the H-I-C absorption layer at least twice.Type: ApplicationFiled: July 16, 2003Publication date: January 20, 2005Inventors: Aaditya Mahajan, Edward Beam, Jose Jiminez, Andrew Ketterson
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Publication number: 20040218275Abstract: A pitch averaging Bragg grating includes a plurality of grating peaks spaced by different pitch values. By selecting the different pitch values to have an average pitch value equal to a target pitch value, the pitch averaging Bragg grating can be made to perform like a constant pitch Bragg grating having a fixed pitch at the target pitch value. The different pitch values can be multiples of the minimum placement resolution of a production tool to be used to produce the Bragg grating. The pitch averaging Bragg grating can be used in place of constant pitch Bragg gratings in optical devices and systems, such as DFB lasers, DBR lasers, optical spectral filters, multi-wavelength laser arrays, and WDM systems.Type: ApplicationFiled: April 30, 2003Publication date: November 4, 2004Applicant: TriQuint Semiconductor, Inc.Inventors: Andrew A. Ketterson, Jose L. Jimenez, Christopher T. Youtsey
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Patent number: 4827320Abstract: A strained In.sub.y Ga.sub.l-y As layer is employed in a GaAs/Al.sub.x Ga.sub.l-x As transistor. Since the bandgap of In.sub.y Ga.sub.l-y As is much smaller than that of GaAs, there is no need for a troublesome large-mole-fraction of aluminum in the Al.sub.x Ga.sub.l-x As layer in order to maintain a large bandgap discontinuity. This and other advantages of the structure set forth result in devices having improved operating characteristics.Type: GrantFiled: September 19, 1986Date of Patent: May 2, 1989Assignee: University of IllinoisInventors: Hadis Morkoc, John Klem, William T. Masselink, Timothy S. Henderson, Andrew A. Ketterson