Abstract: A pair of ground planes arranged in parallel, a dielectric medium disposed in between the pair of ground planes, and a set of at least four signal conductors disposed in the dielectric medium, the set of at least four signal conductors having (i) a first pair of signal conductors arranged proximate to a first ground plane of the pair of ground planes and (ii) a second pair of signal conductors arranged proximate to a second ground plane of the pair of ground planes, each signal conductor of the set of at least four signal conductors configured to carry a respective signal corresponding to a symbol of a codeword of a vector signaling code.

Abstract: A pair of ground planes arranged in parallel, a dielectric medium disposed in between the pair of ground planes, and a set of at least four signal conductors disposed in the dielectric medium, the set of at least four signal conductors having (i) a first pair of signal conductors arranged proximate to a first ground plane of the pair of ground planes and (ii) a second pair of signal conductors arranged proximate to a second ground plane of the pair of ground planes, each signal conductor of the set of at least four signal conductors configured to carry a respective signal corresponding to a symbol of a codeword of a vector signaling code.

Abstract: A pair of ground planes arranged in parallel, a dielectric medium disposed in between the pair of ground planes, and a set of at least four signal conductors disposed in the dielectric medium, the set of at least four signal conductors having (i) a first pair of signal conductors arranged proximate to a first ground plane of the pair of ground planes and (ii) a second pair of signal conductors arranged proximate to a second ground plane of the pair of ground planes, each signal conductor of the set of at least four signal conductors configured to carry a respective signal corresponding to a symbol of a codeword of a vector signaling code.

Abstract: Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between a transmitting device and a receiving device operating at high speed with low power utilization. Communication is performed using group signaling over sets of four wires using a vector signaling code, where each wire of a set carries a low-swing signal that may take on one of four signal values. Topologies and designs of wire sets are disclosed with preferred characteristics for group signaling communications.

Abstract: Conventional methods using signal test patterns to identify wiring errors are difficult to apply to interfaces encoding information as signal state transitions rather than directly as signal states. A system utilizing excitation of wires with selected transition coded patterns and evaluation of received results is described to identify failed wire connections. This approach may be advantageously used to provide fault detection and redundant path selection in systems incorporating stacked chip interconnections using Through Silicon Vias.

Abstract: Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between integrated circuit chips with low power utilization. Communication is performed using group signaling over multiple wires using a vector signaling code, where each wire carries a low-swing signal that may take on more than two signal values.

Abstract: Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between a transmitting device and a receiving device operating at high speed with low power utilization. Communication is performed using group signaling over sets of four wires using a vector signaling code, where each wire of a set carries a low-swing signal that may take on one of four signal values. Topologies and designs of wire sets are disclosed with preferred characteristics for group signaling communications.

Abstract: Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated Simultaneous Switching Output noise. Controller-side and memory-side embodiments of such channel interfaces are disclosed which do not require additional pin count or data transfer cycles, have low power utilization, and introduce minimal additional latency. In some embodiments of the invention, three or more voltage levels are used for signaling.

Abstract: Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between a transmitting device and a receiving device operating at high speed with low power utilization. Communication is performed using group signaling over sets of four wires using a vector signaling code, where each wire of a set carries a low-swing signal that may take on one of four signal values. Topologies and designs of wire sets are disclosed with preferred characteristics for group signaling communications.

Abstract: A communications system receiver is described providing automatic timing adjustment of receive data sampling. A concurrently received clock signal is used as both a reference for generation of internal receiver timing signals, and as an exemplar for adjustment of those timing signals to optimize received data sample timing.

Abstract: Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between integrated circuit chips with low power utilization. Communication is performed using group signaling over multiple wires using a vector signaling code, where each wire carries a low-swing signal that may take on more than two signal values.

Abstract: Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated Simultaneous Switching Output noise. Controller-side and memory-side embodiments of such channel interfaces are disclosed which do not require additional pin count or data transfer cycles, have low power utilization, and introduce minimal additional latency. In some embodiments of the invention, three or more voltage levels are used for signaling.

Abstract: Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between a transmitting device and a receiving device operating at high speed with low power utilization. Communication is performed using group signaling over sets of four wires using a vector signaling code, where each wire of a set carries a low-swing signal that may take on one of four signal values. Topologies and designs of wire sets are disclosed with preferred characteristics for group signaling communications.

Abstract: Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between integrated circuit chips with low power utilization. Communication is performed using group signaling over multiple wires using a vector signaling code, where each wire carries a low-swing signal that may take on more than two signal values.

Abstract: In a high-impedance communications interface, driver energy consumption is proportional to the number of signal transitions. For signals having three or more distinct levels, it is possible for a signal driver to salvage energy from some downward signal transitions and reuse it on some subsequent upward signal transitions. To facilitate this energy-conserving behavior, communication is performed using group signaling over sets of wires using a vector signaling code, with the design and use of the vector signaling code insuring that energy availability is balanced with energy demand.

Abstract: Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated Simultaneous Switching Output noise. Controller-side and memory-side embodiments of such channel interfaces are disclosed which do not require additional pin count or data transfer cycles, have low power utilization, and introduce minimal additional latency. In some embodiments of the invention, three or more voltage levels are used for signaling.

Abstract: Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated Simultaneous Switching Output noise. Controller-side and memory-side embodiments of such channel interfaces are disclosed which do not require additional pin count or data transfer cycles, have low power utilization, and introduce minimal additional latency. In some embodiments of the invention, three or more voltage levels are used for signaling.

Abstract: Conventional methods using signal test patterns to identify wiring errors are difficult to apply to interfaces encoding information as signal state transitions rather than directly as signal states. A system utilizing excitation of wires with selected transition coded patterns and evaluation of received results is described to identify failed wire connections. This approach may be advantageously used to provide fault detection and redundant path selection in systems incorporating stacked chip interconnections using Through Silicon Vias.

Abstract: Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between integrated circuit chips with low power utilization. Communication is performed using group signaling over multiple wires using a vector signaling code, where each wire carries a low-swing signal that may take on more than two signal values.

Abstract: Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated Simultaneous Switching Output noise. Controller-side and memory-side embodiments of such channel interfaces are disclosed which do not require additional pin count or data transfer cycles, have low power utilization, and introduce minimal additional latency. In some embodiments of the invention, three or more voltage levels are used for signaling.