Abstract: A method and various circuit embodiments for low latency initialization of an SRAM are disclosed. In one embodiment, an IC includes an SRAM coupled to at least one functional circuit block. The SRAM includes a number of storage location arranged in rows and columns. The functional circuit block and the SRAM may be in different power domains. Upon initially powering up or a restoration of power, the functional circuit block may assert an initialization signal to begin an initialization process. Responsive to the initialization signal, level shifters may force assertion of various select/enable signals in a decoder associated with the SRAM. Thereafter, initialization data may be written to the SRAM. Writing initialization data may be performed on a row-by-row basis, with all columns in a row being written to substantially simultaneously.

Abstract: A method and various circuit embodiments for low latency initialization of an SRAM are disclosed. In one embodiment, an IC includes an SRAM coupled to at least one functional circuit block. The SRAM includes a number of storage location arranged in rows and columns. The functional circuit block and the SRAM may be in different power domains. Upon initially powering up or a restoration of power, the functional circuit block may assert an initialization signal to begin an initialization process. Responsive to the initialization signal, level shifters may force assertion of various select/enable signals in a decoder associated with the SRAM. Thereafter, initialization data may be written to the SRAM. Writing initialization data may be performed on a row-by-row basis, with all columns in a row being written to substantially simultaneously.

Abstract: A latch circuit. The latch circuit may include an input circuit, a precharge circuit, and a transfer circuit. The precharge circuit may precharge a first node during a first phase of a clock signal. Based on an input signal received at a first logic value, the input signal may drive the first node to a second logic value during the second clock phase. The transfer circuit may include a discharge circuit that is active during an evaluation phase beginning at a delay time subsequent to the clock signal entering the second phase and ending when the clock signal re-enters the first phase. The transfer circuit may also include pull-up and pull-down transistors, one of which may drive a logic value to a second node during the evaluation phase.

Abstract: A latch circuit. The latch circuit may include an input circuit, a precharge circuit, and a transfer circuit. The precharge circuit may precharge a first node during a first phase of a clock signal. Based on an input signal received at a first logic value, the input signal may drive the first node to a second logic value during the second clock phase. The transfer circuit may include a discharge circuit that is active during an evaluation phase beginning at a delay time subsequent to the clock signal entering the second phase and ending when the clock signal re-enters the first phase. The transfer circuit may also include pull-up and pull-down transistors, one of which may drive a logic value to a second node during the evaluation phase.