Patents by Inventor Andrew L. Chanler

Andrew L. Chanler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11232036
    Abstract: Writes to one or more physical storage devices may be blocked after a certain storage consumption threshold (WBT) for each physical storage device. A WBT for certain designated physical storage devices may be applied in addition to, or as an alternative to, determining and applying a user-defined background task mode threshold (UBTT) for certain designated physical storage devices. In some embodiments, the WBT and UBTT for a physical storage device designated for spontaneous de-staging may be a same threshold value. Write blocking management may include, for each designated physical storage device, blocking any writes to the designated physical storage device after a WBT for the designated physical storage device has been reached, and restoring (e.g., unblocking) writes to the designated physical storage device after storage consumption on the physical storage device has been reduced to a storage consumption threshold (WRT) lower than the WBT.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: January 25, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Gabriel Benhanokh, Andrew L. Chanler, Arieh Don
  • Publication number: 20210374017
    Abstract: Snapshots may be managed on a data storage system including logical storage unit including data portions. For a first logical storage unit, a first snapshot pointer structure may be provided including entries, each entry corresponding to a physical storage location at which data is stored for a data portion of the first logical storage unit at a particular point in time. A first virtual snapshot lookup table may be provided for a first portion of the first logical storage unit, the first virtual snapshot lookup table including a plurality of entries, each entry corresponding to a respective data portion of the first logical storage unit and including a reference to a respective entry of the first snapshot pointer structure. The virtual lookup table may correspond to multiple snapshots of the first logical storage unit that have a same value for each data portion of the at least first portion.
    Type: Application
    Filed: May 28, 2020
    Publication date: December 2, 2021
    Applicant: EMC IP Holding Company LLC
    Inventors: Kevin M. Tobin, Andrew L. Chanler, Michael Ferrari, Jeffrey Wilson
  • Patent number: 11188425
    Abstract: Snapshots may be managed on a data storage system including logical storage unit including data portions. For a first logical storage unit, a first snapshot pointer structure may be provided including entries, each entry corresponding to a physical storage location at which data is stored for a data portion of the first logical storage unit at a particular point in time. A first virtual snapshot lookup table may be provided for a first portion of the first logical storage unit, the first virtual snapshot lookup table including a plurality of entries, each entry corresponding to a respective data portion of the first logical storage unit and including a reference to a respective entry of the first snapshot pointer structure. The virtual lookup table may correspond to multiple snapshots of the first logical storage unit that have a same value for each data portion of the at least first portion.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: November 30, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Kevin M. Tobin, Andrew L. Chanler, Michael Ferrari, Jeffrey Wilson
  • Patent number: 11157184
    Abstract: A host system performs I/O processing using metadata for a storage system, where none or some of the metadata is stored on the host system. The host system may be coupled to the global memory of the storage system along a communication path that includes an internal switching fabric of the storage system and does not include a network located externally to the storage system. The host system may exchange communications over the communication path to access indirection layers on the storage system to determine a global memory address of metadata corresponding to an I/O operation. The host system may include a host metadata table of global memory addresses for metadata of logical locations logical devices. The host system may query the host metadata table for a global memory address of metadata corresponding to a logical location specified in an I/O operation.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: October 26, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Andrew L. Chanler, Kevin M. Tobin, Gabi Benhanokh
  • Publication number: 20210248124
    Abstract: A node mask of a global metadata structure entry representing an MD portion in GM may be updated when an entry of a local MD table representing the MD portion is removed in response to receiving an IO operation, without negatively impacting performance of the IO operation. An update process that is independent of the process executing the IO operation may update the node mask so that performance of the IO operation is not negatively affected. In response to the entry for the MD portion being removed from the local MD table, an entry may be added to a queue. The update process may include accessing the entries in the queue, and, for each entry, updating the node mask (e.g., clearing a bit representing the processing node) and removing the entry from the queue.
    Type: Application
    Filed: February 6, 2020
    Publication date: August 12, 2021
    Applicant: EMC IP Holding Company LLC
    Inventors: Kevin M. Tobin, Gabi Benhanokh, Andrew L. Chanler, Jerome J. Cartmell
  • Publication number: 20210124682
    Abstract: Providing global values may include configuring a global memory to include a global counter and configuring processing cores to have private caches each including two sets of buffers, an update toggle and a read toggle. A processing core having a first private cache may perform processing to read a current value for the global counter including determining the current value of the global counter as a mathematical sum of a local counter value and a local delta value from one of the two sets of buffers of the first private cache identified by the read toggle. The processing core may perform processing to modify the global counter by a first amount by updating the local delta value from a specified one of the two set of buffers of the first private cache identified by the update toggle.
    Type: Application
    Filed: October 28, 2019
    Publication date: April 29, 2021
    Applicant: EMC IP Holding Company LLC
    Inventors: Andrew L. Chanler, John Creed, Kaustubh S. Sahasrabudhe
  • Patent number: 10990530
    Abstract: Providing global values may include configuring a global memory to include a global counter and configuring processing cores to have private caches each including two sets of buffers, an update toggle and a read toggle. A processing core having a first private cache may perform processing to read a current value for the global counter including determining the current value of the global counter as a mathematical sum of a local counter value and a local delta value from one of the two sets of buffers of the first private cache identified by the read toggle. The processing core may perform processing to modify the global counter by a first amount by updating the local delta value from a specified one of the two set of buffers of the first private cache identified by the update toggle.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: April 27, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Andrew L. Chanler, John Creed, Kaustubh S. Sahasrabudhe
  • Patent number: 10970210
    Abstract: Physical storage devices may be managed for spontaneous de-staging from a cache, for example, by determining a background task threshold (UBTT), and controlling one or more physical storage devices to use the UBTT instead of the VBTT in determining when to enter background task mode. The determined UBTT may be less than the VBTT, which may cause the physical storage device to enter into background task mode earlier, which means that background tasks like garbage collection and write leveling may be performed more frequently. An ability to turn on and turn off management of physical storage devices for spontaneous de-staging of a cache may be provided. It may be desirable to turn off physical storage device management for spontaneous de-staging, for example, during peak workload hours, to prevent physical storage devices from entering into background task mode more frequently during certain times.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: April 6, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Gabi Benhanokh, Andrew L. Chanler, Arieh Don
  • Publication number: 20210034533
    Abstract: Writes to one or more physical storage devices may be blocked after a certain storage consumption threshold (WBT) for each physical storage device. A WBT for certain designated physical storage devices may be applied in addition to, or as an alternative to, determining and applying a user-defined background task mode threshold (UBTT) for certain designated physical storage devices. In some embodiments, the WBT and UBTT for a physical storage device designated for spontaneous de-staging may be a same threshold value. Write blocking management may include, for each designated physical storage device, blocking any writes to the designated physical storage device after a WBT for the designated physical storage device has been reached, and restoring (e.g., unblocking) writes to the designated physical storage device after storage consumption on the physical storage device has been reduced to a storage consumption threshold (WRT) lower than the WBT.
    Type: Application
    Filed: August 2, 2019
    Publication date: February 4, 2021
    Applicant: EMC IP Holding Company LLC
    Inventors: Gabriel Benhanokh, Andrew L. Chanler, Arieh Don
  • Publication number: 20200349073
    Abstract: Physical storage devices may be managed for spontaneous de-staging from a cache, for example, by determining a background task threshold (UBTT), and controlling one or more physical storage devices to use the UBTT instead of the VBTT in determining when to enter background task mode. The determined UBTT may be less than the VBTT, which may cause the physical storage device to enter into background task mode earlier, which means that background tasks like garbage collection and write leveling may be performed more frequently. An ability to turn on and turn off management of physical storage devices for spontaneous de-staging of a cache may be provided. It may be desirable to turn off physical storage device management for spontaneous de-staging, for example, during peak workload hours, to prevent physical storage devices from entering into background task mode more frequently during certain times.
    Type: Application
    Filed: April 30, 2019
    Publication date: November 5, 2020
    Applicant: EMC IP Holding Company LLC
    Inventors: Gabi Benhanokh, Andrew L. Chanler, Arieh Don
  • Publication number: 20200348867
    Abstract: A host system performs I/O processing using metadata for a storage system, where none or some of the metadata is stored on the host system. The host system may be coupled to the global memory of the storage system along a communication path that includes an internal switching fabric of the storage system and does not include a network located externally to the storage system. The host system may exchange communications over the communication path to access indirection layers on the storage system to determine a global memory address of metadata corresponding to an I/O operation. The host system may include a host metadata table of global memory addresses for metadata of logical locations logical devices. The host system may query the host metadata table for a global memory address of metadata corresponding to a logical location specified in an I/O operation.
    Type: Application
    Filed: April 30, 2019
    Publication date: November 5, 2020
    Applicant: EMC IP Holding Company LLC
    Inventors: Andrew L. Chanler, Kevin M. Tobin, Gabi Benhanokh