Abstract: There is provided an apparatus for cyclical plasma etching of a substrate, the apparatus comprising: a process chamber; a support within the process chamber for receiving the substrate to be etched; a controller for repeatedly applying a dosing step and a bombardment steps respectively; a dosing controller for controlling the flow of a process gas in the dosing step such that the substrate is exposed to a maximum dose of process gas in use of 1000 Langmuirs and said dose is controllable within an accuracy of 1 Langmuir; and a first signal generator coupled to the process chamber and a second signal generator coupled to the support within the process chamber, the first and second signal generators being configured such that in use positions ions of an plasma active species within the process chamber have a substrate bombardment energy in the range of 10 eV to 100 eV which is controllable within an accuracy of 5 eV. There is also provided a method for cyclical plasma etching of a substrate using said apparatus.

Abstract: There is provided an apparatus for cyclical plasma etching of a substrate, the apparatus comprising: a process chamber; a support within the process chamber for receiving the substrate to be etched; a controller for repeatedly applying a dosing step and a bombardment steps respectively; a dosing controller for controlling the flow of a process gas in the dosing step such that the substrate is exposed to a maximum dose of process gas in use of 1000 Langmuirs and said dose is controllable within an accuracy of 1 Langmuir; and a first signal generator coupled to the process chamber and a second signal generator coupled to the support within the process chamber, the first and second signal generators being configured such that in use positions ions of an plasma active species within the process chamber have a substrate bombardment energy in the range of 10 eV to 100 eV which is controllable within an accuracy of 5 eV. There is also provided a method for cyclical plasma etching of a substrate using said apparatus.

Abstract: The present invention provides apparatus for loading a substrate (65) onto a processing surface (61) in a thin-film processing chamber (60). The apparatus includes a support (66) which cooperates with one or more corresponding apertures (62) in the processing surface so as to be movable between an extended position in which the support can support a substrate (65) above the processing surface (61), and a retracted position in which the support is flush with or located below the processing surface (61). The support has a number of limbs (64) which extend radially outwardly from a central hub, at an angle relative to the processing surface. The limbs contact the edges of different sized substrates in use so as to support the substrate in a support plane above the central hub and substantially parallel to the processing surface.

Abstract: A semiconductor device (1) includes a vertical insulated gate field effect device (2) and has a semiconductor body (3) with a first semiconductor region (4) of one conductivity type adjacent one major surface (5). A second semiconductor region (6) of the opposite conductivity type is former within the first region (4) adjacent the surface (5) and a third region (7) forms with the second region (6) a rectifying junction (8) meeting the one major surface (5). A recess (9) extends into the first region (4) from the one major surface (5) so that the second and third regions (6 and 7) abut the recess (9), and an insulated gate (10) is formed within the recess (9) for controlling conduction between the first and third regions (4 and 7) along a conduction channel area (61) of the second region (6).

Abstract: In the manufacture of a large-area electronic device such as a large-area liquid-crystal display device with thin-film address and drive circuitry, a plasma treatment is carried out on a device substrate (4) which is mounted on a supporting electrode (11) facing a perforated gas-feeding electrode (12). A reactive plasma (5) is generated in a space between the electrodes (11, 12) from a mixture of reaction gases which is fed into the space through at least the perforated electrode (12). The mixture of gases comprises a first reaction gas (e.g. SiH.sub.4) which is depleted at a faster rate in the plasma treatment than a second reaction gas (e.g N.sub.2). Through an area (12b) of the perforated electrode, one or more second supply lines (22) feeds a secondary mixture which is richer in the first reaction gas than a primary mixture supplied by a first supply line (21).

Abstract: A semiconductor device (1) includes a vertical insulated gate field effect device (2) and has a semiconductor body (3) with a first semiconductor region (4) of one conductivity type adjacent one major surface (5). A second semiconductor region (6) of the opposite conductivity type is formed within the first region (4) adjacent the surface (5) and a third region (7) forms with the second region (6) a rectifying junction (8) meeting the one major surface (5). A recess (9) extends into the first region (4) from the one major surface (5) so that the second and third regions (6 and 7) abut the recess (9), and an insulated gate (10) is formed within the recess (9) for controlling conduction between the first and third regions (4 and 7) along a conduction channel area (61) of the second region (6).

Abstract: A semiconductor body (3) has a first region (4) of one conductivity type adjacent one major surface (5). A first masking layer (6) comprising at least one first mask window (6a) spaced from a second mask window (6b) is defined on the surface (5). Opposite conductivity type impurities are then introduced through the first masking layer (6) and a second masking layer (8) which is selectively removable with respect to the first masking layer (6) is subsequently provided on the first masking layer and patterned to leave a mask area (8a) covering the first mask window (6a). The semiconductor body (3) is then etched through the second mask window (6b) to define a recess (9) extending into the first region (4) while leaving the introduced impurities beneath the masked first mask window (6a) to form a relatively highly doped second region (7).

Abstract: A semiconductor component (1a) has first and second insulated gate field effect devices (T1 and T2) formed within the same seminconductor body (2). The devices (T1 and T2) have a common first main electrode (D) and an arrangement (20) provides a resistive connection (20b) between a second main electrode (S2)of the second device (T2) and the insulated gate (G1) of the first device (T1). The second device (T2) is formed so as to be more susceptible than the first device (T1) to parasitic bipolar transistor action for causing, when the first and second devices (T1 and T2) are turned off and a voltage exceeding a critical voltage (V.sub.