Abstract: A serial interface unit having an input shift register adapted to receive a serial input data from a serial data stream, and a destination request module. The input shift register converting the serial input data into a parallel input data. The input shift register in communication with at least two processors and the destination request module. The destination request module in communication with one of the at least two processors in response to an input shift register status signal and a processor designation signal, the selected processor adapted to receive the parallel input data.

Abstract: A method and apparatus for communicating transmit and receive data between a digital signal processor and the baseband processing circuitry in a digital communications station such as a digital cellular telephone. The invention utilizes a transmit buffer and a receive buffer for smoothing out the flow of data. TRANSMIT BUFFER EMPTY and RECEIVE BUFFER FULL interrupts indicating the need for data to be retrieved from the transmit buffer or sent to the receive buffer, respectively, are serviced by a DMA with translation circuitry rather than the DSP. The DMA with translation circuitry intercepts the interrupts and services them by transferring data directly to or from the DSP's RAM without disturbing the DSP. The translation circuitry also arbitrates between TRANSMIT BUFFER EMPTY and RECEIVE BUFFER FULL interrupts so as to service the RECEIVE BUFFER FULL interrupts first since they have stricter timing requirements.

Abstract: A buffer design for use in digital signal processing for providing parallel shifting of digital data and serial output of the shifted data. The buffer includes an input shift register for receiving and shifting an input digital word, and one or more parallel shift registers connected to the input shift register for receiving and parallel shifting the shifted digital word output by the input shift register. An output shift register is connected to the parallel shift registers for shifting and serially outputting the shifted data word. The use of parallel shift registers in the inventive buffer allows for a more efficient use of chip surface area in the buffer design, thereby increasing overall chip yield and reducing chip cost.