Abstract: A method of assembling and shaping a laminate panel. An intermediate member is mounted on a lay-up table and a lay-up is assembling by laying a series of plies onto the intermediate member on the lay-up table. The intermediate member and the lay-up are then removed from the lay-up table and placed them on a shaped surface. The lay-up is then forced against the shaped surface, via the intermediate member, in a manner that modifies the shape of the lay-up to form a shaped laminate panel. Finally the shaped laminate panel is removed from the intermediate member. The lay-up table can thus support the flexible intermediate member during assembly, and can be relatively flat to enable the lay-up to assembled by an automated process.

Abstract: A method of assembling and shaping a laminate panel. An intermediate member is mounted on a lay-up table and a lay-up is assembling by laying a series of plies onto the intermediate member on the lay-up table. The intermediate member and the lay-up are then removed from the lay-up table and placed them on a shaped surface. The lay-up is then forced against the shaped surface, via the intermediate member, in a manner that modifies the shape of the lay-up to form a shaped laminate panel. Finally the shaped laminate panel is removed from the intermediate member. The lay-up table can thus support the flexible intermediate member during assembly, and can be relatively flat to enable the lay-up to assembled by an automated process.

Abstract: A method of assembling and shaping a laminate panel. An intermediate member is mounted on a lay-up table and a lay-up is assembling by laying a series of plies onto the intermediate member on the lay-up table. The intermediate member and the lay-up are then removed from the lay-up table and placed them on a shaped surface. The lay-up is then forced against the shaped surface, via the intermediate member, in a manner that modifies the shape of the lay-up to form a shaped laminate panel. Finally the shaped laminate panel is removed from the intermediate member. The lay-up table can thus support the flexible intermediate member during assembly, and can be relatively flat to enable the lay-up to assembled by an automated process.

Abstract: A creep forming tool modifies the shape of an aircraft component in the form of a wing skin portion. The tool includes a shaped surface defined by removable rib boards. The component is forced against the shaped surface, via a reusable intermediate plate. The shape of the shaped surface may be adjusted, if necessary, by replacing the rib boards with boards of a different shape.

Abstract: A method of assembling and shaping a laminate panel. An intermediate member is mounted on a lay-up table and a lay-up is assembling by laying a series of plies onto the intermediate member on the lay-up table. The intermediate member and the lay-up are then removed from the lay-up table and placed them on a shaped surface. The lay-up is then forced against the shaped surface, via the intermediate member, in a manner that modifies the shape of the lay-up to form a shaped laminate panel. Finally the shaped laminate panel is removed from the intermediate member. The lay-up table can thus support the flexible intermediate member during assembly, and can be relatively flat to enable the lay-up to assembled by an automated process.

Abstract: An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and output the data signal detected at the test plate capacitively coupled to the signal terminals. Alternatively, the test plate is coupled to a test transmitter circuit to transmit data signals to signal terminals through the capacitively coupled test plate. A test unit can be coupled to the semiconductor device to evaluate the detected data signal against test criteria. Testing and evaluation is accomplished by capacitively coupling a test plate to a plurality of signal terminals. Data signals transmitted from a signal terminal and detected by the test plate or transmitted from the test plate and detected by the signal terminals are evaluated against a test criteria.

Abstract: A method of creep forming a metallic component is provided. The method includes the steps of applying static loading and cyclic loading and/or vibration to the component during the creep forming thereof to act as a source of additional energy.

Abstract: An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and output the data signal detected at the test plate capacitively coupled to the signal terminals. Alternatively, the test plate is coupled to a test transmitter circuit to transmit data signals to signal terminals through the capacitively coupled test plate. A test unit can be coupled to the semiconductor device to evaluate the detected data signal against test criteria. Testing and evaluation is accomplished by capacitively coupling a test plate to a plurality of signal terminals. Data signals transmitted from a signal terminal and detected by the test plate or transmitted from the test plate and detected by the signal terminals are evaluated against a test criteria.

Abstract: An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and output the data signal detected at the test plate capacitively coupled to the signal terminals. Alternatively, the test plate is coupled to a test transmitter circuit to transmit data signals to signal terminals through the capacitively coupled test plate. A test unit can be coupled to the semiconductor device to evaluate the detected data signal against test criteria. Testing and evaluation is accomplished by capacitively coupling a test plate to a plurality of signal terminals. Data signals transmitted from a signal terminal and detected by the test plate or transmitted from the test plate and detected by the signal terminals are evaluated against a test criteria.

Abstract: An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and output the data signal detected at the test plate capacitively coupled to the signal terminals. Alternatively, the test plate is coupled to a test transmitter circuit to transmit data signals to signal terminals through the capacitively coupled test plate. A test unit can be coupled to the semiconductor device to evaluate the detected data signal against test criteria. Testing and evaluation is accomplished by capacitively coupling a test plate to a plurality of signal terminals. Data signals transmitted from a signal terminal and detected by the test plate or transmitted from the test plate and detected by the signal terminals are evaluated against a test criteria.

Abstract: This invention relates to a process for producing a Simian Immunodeficiency Virus (SIV) encoding a heterologous gene, which process comprises infecting a host cell with a first vector which is capable of producing SIV capsid and a second vector comprising a Human Immunodeficiency Virus type 2 (HIV-2) packaging signal sufficient to package the second vector in the SIV capsid and a heterologous gene capable of being expressed by the vector; and culturing the host cell.

Abstract: A creep forming tool modifies the shape of an aircraft component in the form of a wing skin portion. The tool includes a shaped surface defined by removable rib boards. The component is forced against the shaped surface, via a reusable intermediate plate. The shape of the shaped surface may be adjusted, if necessary, by replacing the rib boards with boards of a different shape.

Abstract: A mechanism for discharging parasitic capacitance at an input of an operational amplifier, which is shared between two stages of a pipelined analog-to-digital converter and/or two channels of signal processing circuitry, before the amplifier configuration of the stages/channels is switched. The discharging act occurs when a short reset pulse is generated between two clock phases. The short reset pulse is applied to a switch connected to the operational amplifier input. When the reset pulse closes the switch, a discharge path is created and any parasitic capacitance at the operational amplifier input is discharged through the path. The discharging of the parasitic capacitance substantially mitigates the memory effect and the problems associated with the memory effect.

Abstract: An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and output the data signal detected at the test plate capacitively coupled to the signal terminals. Alternatively, the test plate is coupled to a test transmitter circuit to transmit data signals to signal terminals through the capacitively coupled test plate. A test unit can be coupled to the semiconductor device to evaluate the detected data signal against test criteria. Testing and evaluation is accomplished by capacitively coupling a test plate to a plurality of signal terminals. Data signals transmitted from a signal terminal and detected by the test plate or transmitted from the test plate and detected by the signal terminals are evaluated against a test criteria.

Abstract: An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and output the data signal detected at the test plate capacitively coupled to the signal terminals. Alternatively, the test plate is coupled to a test transmitter circuit to transmit data signals to signal terminals through the capacitively coupled test plate. A test unit can be coupled to the semiconductor device to evaluate the detected data signal against test criteria. Testing and evaluation is accomplished by capacitively coupling a test plate to a plurality of signal terminals. Data signals transmitted from a signal terminal and detected by the test plate or transmitted from the test plate and detected by the signal terminals are evaluated against a test criteria.

Abstract: An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and output the data signal detected at the test plate capacitively coupled to the signal terminals. Alternatively, the test plate is coupled to a test transmitter circuit to transmit data signals to signal terminals through the capacitively coupled test plate. A test unit can be coupled to the semiconductor device to evaluate the detected data signal against test criteria. Testing and evaluation is accomplished by capacitively coupling a test plate to a plurality of signal terminals. Data signals transmitted from a signal terminal and detected by the test plate or transmitted from the test plate and detected by the signal terminals are evaluated against a test criteria.

Abstract: An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and output the data signal detected at the test plate capacitively coupled to the signal terminals. Alternatively, the test plate is coupled to a test transmitter circuit to transmit data signals to signal terminals through the capacitively coupled test plate. A test unit can be coupled to the semiconductor device to evaluate the detected data signal against test criteria. Testing and evaluation is accomplished by capacitively coupling a test plate to a plurality of signal terminals. Data signals transmitted from a signal terminal and detected by the test plate or transmitted from the test plate and detected by the signal terminals are evaluated against a test criteria.

Abstract: An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random binary sequence generator circuit. The encoded and parallel digital data is coupled through a multiplexer to be serialized in a serializer in a normal mode of operation and the parallel test data is coupled through the multiplexer to be serialized in the serializer in a test mode of operation. Encoded and serial digital data are transmitted to a transmission medium in the normal mode, and serial test data are transmitted to the transmission medium in the test mode. The encoder, the serializer, the sequence generator circuit, and the multiplexer may be fabricated in a single integrated circuit chip. The parallel test data may be parallel pseudo-random binary sequence data. The parallel digital data may include data to generate colors in a visual image.

Abstract: An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and output the data signal detected at the test plate capacitively coupled to the signal terminals. Alternatively, the test plate is coupled to a test transmitter circuit to transmit data signals to signal terminals through the capacitively coupled test plate. A test unit can be coupled to the semiconductor device to evaluate the detected data signal against test criteria. Testing and evaluation is accomplished by capacitively coupling a test plate to a plurality of signal terminals. Data signals transmitted from a signal terminal and detected by the test plate or transmitted from the test plate and detected by the signal terminals are evaluated against a test criteria.

Abstract: An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal terminals of the integrated circuit. The test plate is coupled to a test receiver circuit to receive and output the data signal detected at the test plate capacitively coupled to the signal terminals. Alternatively, the test plate is coupled to a test transmitter circuit to transmit data signals to signal terminals through the capacitively coupled test plate. A test unit can be coupled to the semiconductor device to evaluate the detected data signal against test criteria. Testing and evaluation is accomplished by capacitively coupling a test plate to a plurality of signal terminals. Data signals transmitted from a signal terminal and detected by the test plate or transmitted from the test plate and detected by the signal terminals are evaluated against a test criteria.