Abstract: Electrical overstress protection for high speed applications is provided. In certain embodiments, a method of distributed and customizable electrical overstress protection for a semiconductor die is provided. The method includes configuring a heterogeneous overstress protection array that includes a customizable forward protection circuit electrically connected between a power high pad, a power low pad, and a signal pad and distributed across the semiconductor die, including selecting a number of segmented overstress protection devices from a plurality of available overstress protection devices of the customizable protection circuit.

Abstract: Electrical overstress protection for high speed applications is provided. In certain embodiments, a method of distributed and customizable electrical overstress protection for a semiconductor die is provided. The method includes configuring a heterogeneous overstress protection array that includes a customizable forward protection circuit electrically connected between a power high pad, a power low pad, and a signal pad and distributed across the semiconductor die, including selecting a number of segmented overstress protection devices from a plurality of available overstress protection devices of the customizable protection circuit.

Abstract: Electrical overstress protection for high speed applications, such as integrated multiple subsystem communications, is provided. In certain embodiments, a semiconductor die with distributed and configurable electrical overstress protection is provided. The semiconductor die includes signal pads, a core circuit electrically connected to the signal pads, and a configurable overstress protection array operable to protect the core circuit from electrical overstress at the signal pads. The configurable overstress protection array includes a plurality of segmented overstress protection devices of two or more different device types, and both a number of selected overstress protection devices and a device type of the selected overstress protection devices is programmable. The subsystems configurations are enabled in FinFET technology.

Abstract: Electrical overstress protection for high speed applications, such as integrated multiple subsystem communications, is provided. In certain embodiments, a semiconductor die with distributed and configurable electrical overstress protection is provided. The semiconductor die includes signal pads, a core circuit electrically connected to the signal pads, and a configurable overstress protection array operable to protect the core circuit from electrical overstress at the signal pads. The configurable overstress protection array includes a plurality of segmented overstress protection devices of two or more different device types, and both a number of selected overstress protection devices and a device type of the selected overstress protection devices is programmable. The subsystems configurations are enabled in FinFET technology.