Patents by Inventor Andrew Li

Andrew Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12645910
    Abstract: Methods, systems, and apparatus, including computer-readable media, for scaling neural network architectures on hardware accelerators. A method includes receiving training data and information specifying target computing resources, and performing using the training data, a neural architecture search over a search space to identify an architecture for a base neural network. A plurality of scaling parameter values for scaling the base neural network can be identified, which can include repeatedly selecting a plurality of candidate scaling parameter values, and determining a measure of performance for the base neural network scaled according to the plurality of candidate scaling parameter values, in accordance with a plurality of second objectives including a latency objective. An architecture for a scaled neural network can be determined using the architecture of the base neural network scaled according to the plurality of scaling parameter values.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: June 2, 2026
    Assignee: Google LLC
    Inventors: Andrew Li, Sheng Li, Mingxing Tan, Ruoming Pang, Liqun Cheng, Quoc V. Le, Norman Paul Jouppi
  • Publication number: 20260119505
    Abstract: Systems and methods for uses and/or improvements to executing complex multi-step rule execution against big data. Prompts may be parsed to extract rule sets formed of Boolean expressions. These rules can be executed individually against datasets and the results of the rules can be cached. The cached results can be used upon generation of a compound rule, thereby enabling a simplified execution of custom rules. The techniques further resolve issues involving evaluations of various expression subgroupings and logical operators, while also improving performance by eliminating duplicate rule execution and circular dependencies.
    Type: Application
    Filed: October 25, 2024
    Publication date: April 30, 2026
    Applicant: Capital One Services, LLC
    Inventors: Ravi RANE, Andrew LI, Joshua ZEID, Abhishek GHOSH, Ramesh JITTA
  • Publication number: 20260026003
    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. The channel-material strings directly electrically couple to conductor material of the conductor tier. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises a laterally-outer insulative lining extending longitudinally-along the immediately-laterally-adjacent memory-blocks. The laterally-outer insulative lining has its lowest surface between a top and a bottom of the lowest conductive tier. The laterally-outer insulative lining has its highest surface at or below a lowest surface of the next-lowest conductive tier.
    Type: Application
    Filed: September 26, 2025
    Publication date: January 22, 2026
    Applicant: Micron Technology, Inc.
    Inventors: Andrew Li, Sidhartha Gupta, Adam W. Saxler
  • Patent number: 12453093
    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. The channel-material strings directly electrically couple to conductor material of the conductor tier. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises a laterally-outer insulative lining extending longitudinally-along the immediately-laterally-adjacent memory-blocks. The laterally-outer insulative lining has its lowest surface between a top and a bottom of the lowest conductive tier. The laterally-outer insulative lining has its highest surface at or below a lowest surface of the next-lowest conductive tier.
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: October 21, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Andrew Li, Sidhartha Gupta, Adam W. Saxler
  • Publication number: 20250165731
    Abstract: Implementations described herein relate to methods, systems, and computer-readable media to localize dynamic content. In some implementations, a computer-implemented method includes receiving visual content associated with a game from a first client locale, the visual content including text being represented at the first client locale by a first language, converting the text to generate translated text in at least a second language associated with a second client locale, and storing the translated text in a database in association with the visual content.
    Type: Application
    Filed: January 16, 2025
    Publication date: May 22, 2025
    Applicant: Roblox Corporation
    Inventors: Kyle SPENCE, Peter John PHILLIPS, Craig COLLINS, Pengfei GAO, Xiaochen XU, Alex QUARTULLI, Andrew LI, Andrew Gilmore FRANCIS, Jovanni Antonio CUTIGNI, Shreya RAMAMURTHY
  • Publication number: 20250119869
    Abstract: The present disclosure relates to systems, non-transitory computer-readable media, and methods for automatically addressing emergency situations, customizing emergency user interfaces and options, and managing emergency communications. In particular, in one or more embodiments, the disclosed systems detect a transportation irregularity and generate an emergency assistance user interface based on an emergency severity associated with the transportation irregularity. Based on user interactions with the generated emergency assistance user interface, the disclosed systems generate and send an emergency communication to a remote third-party system.
    Type: Application
    Filed: December 19, 2024
    Publication date: April 10, 2025
    Inventors: Preet Singh Anand, Rohan Ramkrishna Dhaimade, Alyssa Michelle Hitchcock, Andrew Li, Alexandra Elizabeth Michaelides, Kimberley Eileen O'Rourke, Prachi Sharma, Naomi Yarin
  • Publication number: 20250113487
    Abstract: Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an upper portion and a lower portion. The upper portion comprises vertically-alternating first insulating tiers and second insulating tiers that are of different insulative compositions relative one another.
    Type: Application
    Filed: December 12, 2024
    Publication date: April 3, 2025
    Applicant: Micron Technology, Inc.
    Inventors: Collin Howder, M. Jared Barclay, Bhavesh Bhartia, Chet E. Carter, John D. Hopkins, Andrew Li, Haoyu Li, Alyssa N. Scarbrough, Grady S. Waldo
  • Publication number: 20250107094
    Abstract: Some embodiments include an integrated assembly having a first structure containing semiconductor material, and having a second structure contacting the first structure. The first structure has a composition along an interface with the second structure. The composition includes additive to a concentration within a range of from about 1018 atoms/cm3 to about 1021 atoms/cm3. The additive includes one or more of carbon, oxygen, nitrogen and sulfur. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: December 11, 2024
    Publication date: March 27, 2025
    Applicant: Micron Technology, Inc.
    Inventors: Yiping Wang, Andrew Li, Haoyu Li, Matthew J. King, Wei Yeeng Ng, Yongjun Jeff Hu
  • Patent number: 12256546
    Abstract: Some embodiments include an integrated assembly having a first structure containing semiconductor material, and having a second structure contacting the first structure. The first structure has a composition along an interface with the second structure. The composition includes additive to a concentration within a range of from about 1018 atoms/cm3 to about 1021 atoms/cm3. The additive includes one or more of carbon, oxygen, nitrogen and sulfur. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: November 2, 2023
    Date of Patent: March 18, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Yiping Wang, Andrew Li, Haoyu Li, Matthew J. King, Wei Yeeng Ng, Yongjun Jeff Hu
  • Publication number: 20250077833
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for determining an architecture for a task neural network that is configured to perform a particular machine learning task on a target set of hardware resources. When deployed on a target set of hardware, such as a collection of datacenter accelerators, the task neural network may be capable of performing the particular machine learning task with enhanced accuracy and speed.
    Type: Application
    Filed: August 30, 2024
    Publication date: March 6, 2025
    Inventors: Sheng Li, Norman Paul Jouppi, Quoc V. Le, Mingxing Tan, Ruoming Pang, Liqun Cheng, Andrew Li
  • Patent number: 12236207
    Abstract: Implementations described herein relate to methods, systems, and computer-readable media to localize dynamic content. In some implementations, a computer-implemented method includes receiving visual content associated with a game from a first client locale, the visual content including text being represented at the first client locale by a first language, converting the text to generate translated text in at least a second language associated with a second client locale, and storing the translated text in a database in association with the visual content.
    Type: Grant
    Filed: February 20, 2023
    Date of Patent: February 25, 2025
    Assignee: Roblox Corporation
    Inventors: Kyle Spence, Peter John Phillips, Craig Collins, Pengfei Gao, Xiaochen Xu, Alex Quartulli, Andrew Li, Andrew Gilmore Francis, Jovanni Antonio Cutigni, Shreya Ramamurthy
  • Publication number: 20250037768
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed that individually comprise a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Material of the first tiers is sacrificial and of different composition from material of the first tiers. Channel-material strings extend through the first tiers and the second tiers. Conducting material in a lowest of the first tiers is formed that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. A horizontally-elongated trench is formed between immediately-laterally-adjacent of the memory-block regions. The trenches extend downwardly into the conducting material.
    Type: Application
    Filed: October 18, 2024
    Publication date: January 30, 2025
    Applicant: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, John D. Hopkins, M. Jared Barclay, Andrew Li, Aireus Christensen
  • Patent number: 12207223
    Abstract: The present disclosure relates to systems, non-transitory computer-readable media, and methods for automatically addressing emergency situations, customizing emergency user interfaces and options, and managing emergency communications. In particular, in one or more embodiments, the disclosed systems detect a transportation irregularity and generate an emergency assistance user interface based on an emergency severity associated with the transportation irregularity. Based on user interactions with the generated emergency assistance user interface, the disclosed systems generate and send an emergency communication to a remote third-party system.
    Type: Grant
    Filed: November 28, 2023
    Date of Patent: January 21, 2025
    Assignee: Lyft, Inc.
    Inventors: Preet Singh Anand, Rohan Ramkrishna Dhaimade, Alyssa Michelle Hitchcock, Andrew Li, Alexandra Elizabeth Michaelides, Kimberley Eileen O'Rourke, Prachi Sharma, Naomi Yarin
  • Patent number: 12200929
    Abstract: Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an upper portion and a lower portion. The upper portion comprises vertically-alternating first insulating tiers and second insulating tiers that are of different insulative compositions relative one another.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: January 14, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Collin Howder, M. Jared Barclay, Bhavesh Bhartia, Chet E. Carter, John D. Hopkins, Andrew Li, Haoyu Li, Alyssa N. Scarbrough, Grady S. Waldo
  • Patent number: 12159674
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed that individually comprise a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Material of the first tiers is sacrificial and of different composition from material of the first tiers. Channel-material strings extend through the first tiers and the second tiers. Conducting material in a lowest of the first tiers is formed that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. A horizontally-elongated trench is formed between immediately-laterally-adjacent of the memory-block regions. The trenches extend downwardly into the conducting material.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: December 3, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, John D. Hopkins, M. Jared Barclay, Andrew Li, Aireus Christensen
  • Patent number: 12131244
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for determining an architecture for a task neural network that is configured to perform a particular machine learning task on a target set of hardware resources. When deployed on a target set of hardware, such as a collection of datacenter accelerators, the task neural network may be capable of performing the particular machine learning task with enhanced accuracy and speed.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: October 29, 2024
    Assignee: Google LLC
    Inventors: Sheng Li, Norman Paul Jouppi, Quoc V. Le, Mingxing Tan, Ruoming Pang, Liqun Cheng, Andrew Li
  • Publication number: 20240274198
    Abstract: A memory array comprising laterally-spaced memory blocks individually comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The laterally-spaced memory blocks in a lower one of the conductive tiers comprises elemental-form metal that extends longitudinally-along the laterally-spaced memory blocks proximate laterally -outer sides of the laterally-spaced memory blocks. A metal silicide or a metal-germanium compound is directly against laterally-inner sides of the elemental-form metal in the lower conductive tier and that extends longitudinally-along the laterally-spaced memory blocks in the lower conductive tier. The metal of the metal silicide or of the metal-germanium compound is the same as that of the elemental-form metal. Other embodiments, including method, are disclosed.
    Type: Application
    Filed: April 23, 2024
    Publication date: August 15, 2024
    Applicant: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, John D. Hopkins, Andrew Li, Alyssa N. Scarbrough
  • Publication number: 20240221104
    Abstract: Disclosed is a method for identifying, in real time, a transportation arrangement between a requestor and a provider that could benefit from a re-matching of the requestor with another provider. A system may match a provider with a requestor to complete a request for transportation from the requestor. The system may monitor a progress of the provider to a pickup location as specified in the request. Based on the monitored progress, the system may determine if the provider is making sufficient progress towards the pickup location. In some examples, the system may determine that the matching of the provider with the requestor is eligible for cancellation because the provider is not making sufficient progress towards the pickup location. The system may cancel the matching and then match another provider with the requestor to continue to make progress towards completing the transportation request.
    Type: Application
    Filed: January 6, 2024
    Publication date: July 4, 2024
    Inventors: Snir Kodesh, Andrew Li, Desmond Mawuko Torkornoo, Naomi Yarin
  • Publication number: 20240206175
    Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers directly above a conductor tier. The first tiers comprise sacrificial material and the second tiers comprise non-sacrificial material that is of different composition from that of the sacrificial material. The stack comprises horizontally-elongated trenches extending through the first tiers and the second tiers and are individually between immediately-laterally-adjacent memory-block regions. Channel-material strings are formed that extend through the first and second tiers in the memory-block regions. Through the horizontally-elongated trenches, the sacrificial material is replaced with conductive material that comprises control-gate lines in the memory-block regions.
    Type: Application
    Filed: December 14, 2023
    Publication date: June 20, 2024
    Applicant: Micron Technology, Inc.
    Inventors: Sidhartha Gupta, Adam W. Saxler, Andrew Li, John D. Hopkins
  • Patent number: 11996151
    Abstract: A memory array comprising laterally-spaced memory blocks individually comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The laterally-spaced memory blocks in a lower one of the conductive tiers comprises elemental-form metal that extends longitudinally-along the laterally-spaced memory blocks proximate laterally-outer sides of the laterally-spaced memory blocks. A metal silicide or a metal-germanium compound is directly against laterally-inner sides of the elemental-form metal in the lower conductive tier and that extends longitudinally-along the laterally-spaced memory blocks in the lower conductive tier. The metal of the metal silicide or of the metal-germanium compound is the same as that of the elemental-form metal. Other embodiments, including method, are disclosed.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: May 28, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, John D. Hopkins, Andrew Li, Alyssa N. Scarbrough