Abstract: A media marker mechanism may be used to send, to a cloud service, up-to-date context regarding playback of a media content stream on a user device. The cloud service may insert a media content item into a media content stream and/or combine media content items into a media content stream. The cloud service may implement the media marker mechanism to tag a content item with metadata that can be read by the user device. The user device can play the streaming media content and, when the tagged content item plays, read the metadata and send it to the cloud service. The cloud service can use the metadata to enrich the media content delivery by, for example, providing a companion image that the user device can display while paying the tagged content item, providing a link to make the companion image clickable, handling requests referring to the media content, etc.

Abstract: Aspects of the subject technology provide for generation of a self-voice signal by an electronic device that is operating in an active noise cancellation mode. In this way, during a phone call, a video conference, or while listening to audio content, a user of the electronic device may benefit from active cancellation of ambient noise while still being able to hear their own voice when they speak. In various implementations described herein, the concurrent self-voice and automatic noise cancellation features are facilitated by accelerometer-based control of sidetone and/or active noise cancellation operations.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for performing neural architecture search for machine learning models. In one aspect, a method comprises receiving training data for a machine learning, generating a plurality of candidate neural networks for performing the machine learning task, wherein each candidate neural network comprises a plurality of instances of a layer block composed of a plurality of layers, for each candidate neural network, selecting a respective type for each of the plurality of layers from a set of layer types that comprises, training the candidate neural network and evaluating performance scores for the trained candidate neural networks as applied to the machine learning task, and determining a final neural network for performing the machine learning task based at least on the performance scores for the candidate neural networks.

Abstract: A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.

Abstract: Methods and systems are provided for a spatialized display of chat messages within a messaging platform. In an example method, a computing device displays a spatial chat user interface (UI) including a virtual background and one or more spatialized avatars overlaid on the virtual background. The computing device receives chat messages sent by a participant and displays, adjacent to the spatialized avatar representing the participant, chat bubbles having a first appearance. The computing device displays chat bubbles for other participants having a second appearance. The computing device receives one or more additional chat messages sent by the participant. The computing device displays additional chat bubbles corresponding to the additional chat messages having a third appearance and updates the appearance of the initial chat bubbles to a fourth appearance.

Abstract: Techniques are described for maintaining contextual data to support content-related actions. In an example, a system stories second content at a source. The source is associated with first content. The system sends, to a device, an object that indicates the first content. From the device at a first time, the system receives first data indicating a first request for the second content and including source information that indicates the source. From the device at a second time, the system receives second data indicating a second request for the second content, the second data including the source information, the first data and the second data received at a frequency indicated by the object. The system determines that the requests are associated with the first content based on the source information included in the received data, and stores third data indicating a presentation of the first content by the device.

Abstract: Aspects of the subject technology provide for generation of a self-voice signal by an electronic device that is operating in an active noise cancellation mode. In this way, during a phone call, a video conference, or while listening to audio content, a user of the electronic device may benefit from active cancellation of ambient noise while still being able to hear their own voice when they speak. In various implementations described herein, the concurrent self-voice and automatic noise cancellation features are facilitated by accelerometer-based control of sidetone and/or active noise cancellation operations.

Abstract: Various methods of making low-tortuosity electrodes are disclosed. In some embodiments, the low-tortuosity electrodes have a tortuosity of less than 2.0 or 1.4 and include battery-active material and solid electrolyte with the solid electrolyte having channels therein that are vertically aligned. A solid-state lithium-ion battery electrode is also disclosed.

Abstract: Method for measuring misalignment between at least two layers of an integrated circuit. The method includes applying a current between a plurality of probe members in a first layer, wherein a first probe member and a second probe member of the plurality of probe members are substantially aligned along a first axis and partially overlap an overlay target in a second layer, measuring a voltage across the plurality of probe members wherein at least a voltage across the first probe member and a third probe member disposed perpendicular to the first axis and a voltage across the second probe member and the third probe member are measured, and determining an amount of misalignment between the first layer and the second layer along at least one of the first axis and the second axis based on the measuring steps.

Abstract: A system, a method and a computer program product for analyzing a circuit design provide for discretizing the circuit design into a series of pixels. A fraction of at least one constituent material is determined for each pixel. A deflection is also determined for each pixel. The deflection is predicated upon a planarizing of the pixel, and it is calculated while utilizing an algorithm that includes the fraction of the at least one constituent material. A series of deflections for the series of pixels may be mapped and evaluated.

Abstract: A system, a method and a computer program product for analyzing a circuit design provide for discretizing the circuit design into a series of pixels. A fraction of at least one constituent material is determined for each pixel. A deflection is also determined for each pixel. The deflection is predicated upon a planarizing of the pixel, and it is calculated while utilizing an algorithm that includes the fraction of the at least one constituent material. A series of deflections for the series of pixels may be mapped and evaluated.

Abstract: Method for measuring misalignment between at least two layers of an integrated circuit. The method includes applying a current between a plurality of probe members in a first layer, wherein a first probe member and a second probe member of the plurality of probe members are substantially aligned along a first axis and partially overlap an overlay target in a second layer, measuring a voltage across the plurality of probe members wherein at least a voltage across the first probe member and a third probe member disposed perpendicular to the first axis and a voltage across the second probe member and the third probe member are measured, and determining an amount of misalignment between the first layer and the second layer along at least one of the first axis and the second axis based on the measuring steps.

Abstract: The systems and methods enable the determination of the magnitude and direction of overlay of at least two elements in two layers. Overlay measurements along two axes can be obtained using four probe pads and without requiring a decoder. Overlay measurements along a single axis can be obtained using three probe pads and without requiring a decoder. The systems and methods according to this invention require less space and are more time efficient than conventional measurement structures. In the systems and methods of this invention, offsets in a direction are calculated from resistance measurements.

Abstract: A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse element is positioned external to the insulator, with a gap juxtaposed between the insulator and the fuse element. The interface wall further comprises a first side wall, a second side wall, and an inner wall, wherein the inner wall is disposed within the gap. The fuse electrodes are diametrically opposed to one another, and the fuse element is perpendicularly disposed above the fuse electrodes. The fuse element is either electroplatted, electroless plated, or is an ultra thin fuse.

Abstract: A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse element is positioned external to the insulator, with a gap juxtaposed between the insulator and the fuse element. The interface wall further comprises a first side wall, a second side wall, and an inner wall, wherein the inner wall is disposed within the gap. The fuse electrodes are diametrically opposed to one another, and the fuse element is perpendicularly disposed above the fuse electrodes. The fuse element is either electroplatted, electroless plated, or is an ultra thin fuse.

Abstract: A method of repeatedly exposing a pattern across a wafer in a sequential stepping process is disclosed. The pattern that is exposed includes at least one alignment mark. Each time the exposing process is repeated, the current exposure overlaps a portion of the wafer where the pattern was previously exposed and thereby erases a previously exposed alignment mark by re-exposing an area of the wafer where the previously exposed alignment mark was located. After the exposing process is repeated across the wafer, alignment marks remain only in the last exposed areas of the wafer.

Abstract: The systems and methods enable the determination of the magnitude and direction of overlay of at least two elements in two layers. Overlay measurements along two axes can be obtained using four probe pads and without requiring a decoder. Overlay measurements along a single axis can be obtained using three probe pads and without requiring a decoder. The systems and methods according to this invention require less space and are more time efficient than conventional measurement structures. In the systems and methods of this invention, offsets in a direction are calculated from resistance measurements.

Abstract: A method of repeatedly exposing a pattern across a wafer in a sequential stepping process is disclosed. The pattern that is exposed includes at least one alignment mark. Each time the exposing process is repeated, the current exposure overlaps a portion of the wafer where the pattern was previously exposed and thereby erases a previously exposed alignment mark by re-exposing an area of the wafer where the previously exposed alignment mark was located. After the exposing process is repeated across the wafer, alignment marks remain only in the last exposed areas of the wafer.

Abstract: An alignment mark structure for use upon a semiconductor substrate is disclosed. In an exemplary embodiment, the alignment mark structure includes a plurality of segments arranged in an alignment pattern, with each of the plurality of segments being formed from a base pattern created on the substrate. The base pattern includes a plurality of sizes, wherein each of the plurality of sizes of the base pattern is repeated throughout an entire length of each of the plurality of segments.

Abstract: An alignment mark structure for use upon a semiconductor substrate is disclosed. In an exemplary embodiment, the alignment mark structure includes a plurality of segments arranged in an alignment pattern, with each of the plurality of segments being formed from a base pattern created on the substrate. The base pattern includes a plurality of sizes, wherein each of the plurality of sizes of the base pattern is repeated throughout an entire length of each of the plurality of segments.