Abstract: In accordance with the teachings of this invention a novel method and apparatus is taught which provides for the stabilizing of an output signal through an output circuit having a compensation circuit coupled with an output capacitor, such that the compensation circuit is configured to compensate for an equivalent series resistance of the output capacitor. The compensation circuit compensates for the equivalent series resistance by providing a shift in a phase of the output signal to stabilize the output signal. The shift in phase is accomplished through the addition of a second zero at a second zero frequency to stabilize the output signal. The second zero is added such that the second zero frequency is closer to a first pole frequency than a first zero frequency, where the first pole frequency is proportional to the equivalent series resistance and the first zero is proportional to the output capacitor.

Abstract: In accordance with the teachings of this invention a novel method and apparatus is taught which provides for the stabilizing of an output signal through an output circuit having a compensation circuit coupled with an output capacitor, such that the compensation circuit is configured to compensate for an equivalent series resistance of the output capacitor. The compensation circuit compensates for the equivalent series resistance by providing a shift in a phase of the output signal to stabilize the output signal. The shift in phase is accomplished through the addition of a second zero at a second zero frequency to stabilize the output signal. The second zero is added such that the second zero frequency is closer to a first pole frequency than a first zero frequency, where the first pole frequency is proportional to the equivalent series resistance and the first zero is proportional to the output capacitor.

Abstract: A start-up circuit for voltage regulators includes a depletion mode field effect transistor (FET) having a drain electrically coupled to an input voltage, a source electrically coupled to the voltage regulator power supply input terminal and to a voltage corresponding to an output voltage of the voltage regulator, a body at a fixed voltage, and a gate electrically coupled to the output of a comparator. At start-up, the voltage regulator is powered through the FET. The drain current is self-limiting, preventing the source of the FET from rising to the level of the input voltage. When the rising output voltage of the regulator reaches a level that can operate the regulator control circuit, the comparator grounds the gate of the FET to turn off the FET, and the voltage regulator operates off of its own output. Virtually no power is dissipated in the FET during steady-state operation of the regulator.