Abstract: A first and second phase-locked loop each having their frequency of operation under programmable control by changing the divider ratio. A single programming word contains the divider ratio for the first phase-locked loop and addressing bits which address a plurality of auxiliary registers for changing the divider ratio of the second phase-locked loop. In a cellular telephone, this allows the digital signal processor to change from receive to transmit mode or from one transmit mode or from one frequency to another utilizing a single command word.

Abstract: A system and method for speed-up of the frequency switching time of a circuit, generally a voltage controlled oscillator having an operating frequency controlling input terminal. A first control circuit is coupled to the frequency controlling input terminal for maintaining the operating frequency of the oscillator at its first selected operating frequency. Circuitry is provided which is responsive to a directed change from the first operating frequency of the oscillator to a second different operating frequency of the oscillator to apply a voltage to the input terminal determined by the size of the directed change in the operating frequency and for a predetermined time period. This circuitry includes a switch coupled to the input terminal, a charge pump coupled to the switch and remote from the input terminal and a timer controlling the current output of the charge pump and the switch. The output of the charge pump is a current which is converted to a voltage.

Abstract: A method of providing low energy consumption ultrafast lock time in a mobile communication system normally operating at slower lock times and requiring occasional ultrafast lock times when switching from the transmit mode to the receive mode and/or from the receive mode to the transmit mode. There are provided a normally operating PLL and a normally disabled DDS. Responsive to a requirement for the ultrafast lock time, the DDS is enabled and substituted for the PLL. Subsequently, responsive to removal of the requirement for the ultrafast lock time, the PLL is substituted for the DDS and the DDS is disabled. When the transmit and/or receive mode requires a frequency above the capability of the DDS, a mixer is added for mixing the output of the DDS with a signal having stable reference frequency to obtain a frequency equal to the sum of frequencies of the DDS output and the stable reference signal.

Abstract: A system and method for providing hard handoff in a mobile communication system wherein there are provided a plurality of spaced apart base stations, each base station equipped for communication with mobile stations at a different frequency from the other of the base stations and a mobile device for intermittent communication with one of the base stations. The mobile device includes a first normally operating circuit, preferably a PLL, for providing an operating frequency at the mobile device having a relatively slow tuning period for communication with the one of the base stations and second normally non-operating circuitry, preferably a DDS, for providing a frequency different from the frequency for communication with the one of the base stations having a rapid tuning period relative to the first circuitry.

Abstract: An electronic system, such as a wireless telephone handset (10), having multiple voltage-controlled oscillators (26, 28) so that the system can operate in a selected one of multiple frequency bands, is disclosed. Each of the voltage-controlled oscillators (26, 28) is associated with one of multiple loop filters (32, 34), which filter the control voltage (CP1, CP2) responsive to which the frequency of oscillation of the voltage-controlled oscillators (26, 28) controlled. Only one of the voltage-controlled oscillators (26, 28) is enabled at any one time, responsive to a control signal (VCOSEL). Synthesizer circuitry (30) includes a phase detector (44) which is coupled to a common node (VCOCLK) at which outputs of the voltage-controlled oscillators (26, 28) are coupled; the phase detector (44) compares the phase of this signal (VCODIV) to a reference signal (REFDIV) based on a reference clock (REFCLK), and controls a charge pump (46) accordingly.