Abstract: Disclosed is a system including a memory device having a plurality of physical memory segments and a processing device to perform operations that include, responsive to detecting a failure of a memory operation associated with a physical memory segment of the plurality of physical memory segments, quarantining the physical memory segment, responsive to quarantining the physical memory segment, performing one or more scanning operations on the physical memory segment, and determining, based on results of the one or more scanning operations, a viability status of the physical memory segment, wherein the viability status indicates an ability of the physical memory segment to store data.

Abstract: Devices, methods, and media are described for runtime memory allocation to avoid defects. One embodiment includes assigning a plurality of memory blocks of a memory sub-system to a plurality of erase groups, such that each erase group of the plurality of erase groups comprises two or more memory blocks of the plurality of memory blocks. A bad block association is determined for each erase group of the plurality of erase groups. Prior to a memory condition being met, memory resources of the memory sub-system are allocated by erase group based on a first set of criteria which are based at least in part on the bad block association for each erase group in order to prioritize use of erase groups with fewer bad blocks.

Abstract: Disclosed is a system including a memory device having a plurality of physical memory segments and a processing device to perform operations that include, responsive to detecting a failure of a memory operation associated with a physical memory segment of the plurality of physical memory segments, quarantining the physical memory segment, responsive to quarantining the physical memory segment, performing one or more scanning operations on the physical memory segment, and determining, based on results of the one or more scanning operations, a viability status of the physical memory segment, wherein the viability status indicates an ability of the physical memory segment to store data.

Abstract: An apparatus includes a component coupleable to a memory device. The component can be configured to analyze a plurality of sets of memory cells of the memory device to determine quality attributes associated with the plurality of sets of memory cells and assign grades to one or more sets of the memory cells based, at least in part, on the determined quality attributes. The component can be configured to allocate at least one of the plurality of sets of memory cells for use by the memory device based, at least in part, on the assigned grade associated with the one or more sets of the memory cells.

Abstract: Disclosed is a system including a memory device having a plurality of physical memory segments and a processing device to perform operations that include, responsive to detecting a failure of a memory operation associated with a physical memory segment of the plurality of physical memory segments, quarantining the physical memory segment, responsive to quarantining the physical memory segment, performing one or more scanning operations on the physical memory segment, and determining, based on results of the one or more scanning operations, a viability status of the physical memory segment, wherein the viability status indicates an ability of the physical memory segment to store data.

Abstract: Aspects of the present disclosure provide systems and methods for improved power loss protection in a memory sub-system of a device. In particular, a power loss protection component allocates a portion of the memory sub-system to non-volatile memory. Responsive to detecting a trigger event at the device, wherein the trigger event may include asynchronous power loss of the device, the power loss protection component detects data written to a volatile cache of the memory sub-system, retrieves the data from the volatile cache, and writes the data to the portion of the memory sub-system allocated to the non-volatile memory.

Abstract: Aspects of the present disclosure provide systems and methods for improved power loss protection in a memory sub-system of a device. In particular, a power loss protection component allocates a portion of the memory sub-system to non-volatile memory. Responsive to detecting a trigger event at the device, wherein the trigger event may include asynchronous power loss of the device, the power loss protection component detects data written to a volatile cache of the memory sub-system, retrieves the data from the volatile cache, and writes the data to the portion of the memory sub-system allocated to the non-volatile memory.

Abstract: Disclosed is a system including a memory device having a plurality of physical memory segments and a processing device to perform operations that include, responsive to detecting a failure of a memory operation associated with a physical memory segment of the plurality of physical memory segments, quarantining the physical memory segment, responsive to quarantining the physical memory segment, performing one or more scanning operations on the physical memory segment, and determining, based on results of the one or more scanning operations, a viability status of the physical memory segment, wherein the viability status indicates an ability of the physical memory segment to store data.

Abstract: Devices, methods, and media are described for runtime memory allocation to avoid defects. One embodiment includes assigning a plurality of memory blocks of a memory sub-system to a plurality of erase groups, such that each erase group of the plurality of erase groups comprises two or more memory blocks of the plurality of memory blocks. A bad block association is determined for each erase group of the plurality of erase groups. Prior to a memory condition being met, memory resources of the memory sub-system are allocated by erase group based on a first set of criteria which are based at least in part on the bad block association for each erase group in order to prioritize use of erase groups with fewer bad blocks.

Abstract: Devices, methods, and media are described for runtime memory allocation to avoid defects. One embodiment includes assigning a plurality of memory blocks of a memory sub-system to a plurality of erase groups, such that each erase group of the plurality of erase groups comprises two or more memory blocks of the plurality of memory blocks. A bad block association is determined for each erase group of the plurality of erase groups. Prior to a memory condition being met, memory resources of the memory sub-system are allocated by erase group based on a first set of criteria which are based at least in part on the bad block association for each erase group in order to prioritize use of erase groups with fewer bad blocks.

Abstract: An apparatus includes a component coupleable to a memory device. The component can be configured to analyze a plurality of sets of memory cells of the memory device to determine quality attributes associated with the plurality of sets of memory cells and assign grades to one or more sets of the memory cells based, at least in part, on the determined quality attributes. The component can be configured to allocate at least one of the plurality of sets of memory cells for use by the memory device based, at least in part, on the assigned grade associated with the one or more sets of the memory cells.

Abstract: An apparatus includes a component coupleable to a memory device. The component can be configured to analyze a plurality of sets of memory cells of the memory device to determine quality attributes associated with the plurality of sets of memory cells and assign grades to one or more sets of the memory cells based, at least in part, on the determined quality attributes. The component can be configured to allocate at least one of the plurality of sets of memory cells for use by the memory device based, at least in part, on the assigned grade associated with the one or more sets of the memory cells.

Abstract: In one embodiment, a method is operable in an over-provisioned storage device comprising a cache region and a main storage region. The method includes compressing incoming data, generating a compression parameter for the compressed data, and storing at least a portion of the compressed data in chunks in the main storage region of the storage device. The method also includes predicting when to store other chunks of the compressed data in the cache region based on the compression parameter.

Abstract: An apparatus includes a component coupleable to a memory device. The component can be configured to analyze a plurality of sets of memory cells of the memory device to determine quality attributes associated with the plurality of sets of memory cells and assign grades to one or more sets of the memory cells based, at least in part, on the determined quality attributes. The component can be configured to allocate at least one of the plurality of sets of memory cells for use by the memory device based, at least in part, on the assigned grade associated with the one or more sets of the memory cells.

Abstract: Devices, methods, and media are described for runtime memory allocation to avoid defects. One embodiment includes assigning a plurality of memory blocks of a memory sub-system to a plurality of erase groups, such that each erase group of the plurality of erase groups comprises two or more memory blocks of the plurality of memory blocks. A bad block association is determined for each erase group of the plurality of erase groups. Prior to a memory condition being met, memory resources of the memory sub-system are allocated by erase group based on a first set of criteria which are based at least in part on the bad block association for each erase group in order to prioritize use of erase groups with fewer bad blocks.

Abstract: Aspects of the present disclosure provide systems and methods for improved power loss protection in a memory sub-system of a device. In particular, a power loss protection component allocates a portion of the memory sub-system to non-volatile memory. Responsive to detecting a trigger event at the device, wherein the trigger event may include asynchronous power loss of the device, the power loss protection component detects data written to a volatile cache of the memory sub-system, retrieves the data from the volatile cache, and writes the data to the portion of the memory sub-system allocated to the non-volatile memory.

Abstract: Aspects of the present disclosure provide systems and methods for improved power loss protection in a memory sub-system of a device. In particular, a power loss protection component allocates a portion of the memory sub-system to non-volatile memory. Responsive to detecting a trigger event at the device, wherein the trigger event may include asynchronous power loss of the device, the power loss protection component detects data written to a volatile cache of the memory sub-system, retrieves the data from the volatile cache, and writes the data to the portion of the memory sub-system allocated to the non-volatile memory.

Abstract: Aspects of the present disclosure provide systems and methods for improved power loss protection in a memory sub-system of a device. In particular, a power loss protection component allocates a portion of the memory sub-system to non-volatile memory. Responsive to detecting a trigger event at the device, wherein the trigger event may include asynchronous power loss of the device, the power loss protection component detects data written to a volatile cache of the memory sub-system, retrieves the data from the volatile cache, and writes the data to the portion of the memory sub-system allocated to the non-volatile memory.

Abstract: A method for data steering in tiered storage is described. In one embodiment, the method includes ranking storage areas of a storage device according to latency of access. In some embodiments, the storage areas include at least a first storage area and a second storage area. The method includes identifying first data at the storage device, passing a portion of the first data through a compression algorithm, and analyzing a result of passing the portion of the first data through the compression algorithm. In some cases, the result includes a score of compression savings associated with the portion of the first data. If the result satisfies a threshold associated with the first storage area, the first data is stored in the first storage area. If the result satisfies a threshold associated with the second storage area, the first data is stored in the second storage area.

Abstract: Implementations disclosed herein provide for increasing storage drive performance by reserving a region of user-writeable storage space on a storage medium for overprovisioning uses, including performance-enhancing functions. Until a capacity condition of the storage drive is satisfied, write operations targeting the reserved region are written to another equal-sized region that does not contain user data.