Patents by Inventor Andrew M. Lever
Andrew M. Lever has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8373249Abstract: The present invention provides a method and apparatus for a programmable capacitor associated with an input/output pad in the semiconductor device. The apparatus includes a semiconductor die having an upper surface, a first capacitor deployed above the upper surface of the semiconductor die, a separation layer deployed above the first capacitor, and a bond pad deployed above the separation layer such that at least a portion of the bond pad lies above the first capacitor.Type: GrantFiled: January 24, 2011Date of Patent: February 12, 2013Assignee: Micron Technology, Inc.Inventors: Sion C. Quinlan, Bryan Almond, Ken S. Hunt, Andrew M. Lever, Joe A. Ward
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Patent number: 8321732Abstract: An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random binary sequence generator circuit. The encoded and parallel digital data is coupled through a multiplexer to be serialized in a serializer in a normal mode of operation and the parallel test data is coupled through the multiplexer to be serialized in the serializer in a test mode of operation. Encoded and serial digital data are transmitted to a transmission medium in the normal mode, and serial test data are transmitted to the transmission medium in the test mode. The encoder, the serializer, the sequence generator circuit, and the multiplexer may be fabricated in a single integrated circuit chip. The parallel test data may be parallel pseudo-random binary sequence data. The parallel digital data may include data to generate colors in a visual image.Type: GrantFiled: September 16, 2011Date of Patent: November 27, 2012Assignee: Micron Technology, Inc.Inventors: David J. Warner, Ken S. Hunt, Andrew M. Lever
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Publication number: 20120011290Abstract: An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random binary sequence generator circuit. The encoded and parallel digital data is coupled through a multiplexer to be serialized in a serializer in a normal mode of operation and the parallel test data is coupled through the multiplexer to be serialized in the serializer in a test mode of operation. Encoded and serial digital data are transmitted to a transmission medium in the normal mode, and serial test data are transmitted to the transmission medium in the test mode. The encoder, the serializer, the sequence generator circuit, and the multiplexer may be fabricated in a single integrated circuit chip. The parallel test data may be parallel pseudo-random binary sequence data. The parallel digital data may include data to generate colors in a visual image.Type: ApplicationFiled: September 16, 2011Publication date: January 12, 2012Inventors: David J. Warner, Ken S. Hunt, Andrew M. Lever
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Patent number: 8024388Abstract: An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random binary sequence generator circuit. The encoded and parallel digital data is coupled through a multiplexer to be serialized in a serializer in a normal mode of operation and the parallel test data is coupled through the multiplexer to be serialized in the serializer in a test mode of operation. Encoded and serial digital data are transmitted to a transmission medium in the normal mode, and serial test data are transmitted to the transmission medium in the test mode. The encoder, the serializer, the sequence generator circuit, and the multiplexer may be fabricated in a single integrated circuit chip. The parallel test data may be parallel pseudo-random binary sequence data. The parallel digital data may include data to generate colors in a visual image.Type: GrantFiled: October 6, 2008Date of Patent: September 20, 2011Assignee: Micron Technology, Inc.Inventors: David J. Warner, Ken S. Hunt, Andrew M. Lever
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Publication number: 20110117716Abstract: The present invention provides a method and apparatus for a programmable capacitor associated with an input/output pad in the semiconductor device. The apparatus includes a semiconductor die having an upper surface, a first capacitor deployed above the upper surface of the semiconductor die, a separation layer deployed above the first capacitor, and a bond pad deployed above the separation layer such that at least a portion of the bond pad lies above the first capacitor.Type: ApplicationFiled: January 24, 2011Publication date: May 19, 2011Applicant: Micron Technology, Inc.Inventors: Sion C. Quinlan, Bryan Almond, Ken S. Hunt, Andrew M. Lever, Joe A. Ward
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Patent number: 7879649Abstract: The present invention provides a method and apparatus for a programmable capacitor associated with an input/output pad in the semiconductor device. The apparatus includes a semiconductor die having an upper surface, a first capacitor deployed above the upper surface of the semiconductor die, a separation layer deployed above the first capacitor, and a bond pad deployed above the separation layer such that at least a portion of the bond pad lies above the first capacitor.Type: GrantFiled: September 22, 2009Date of Patent: February 1, 2011Assignee: Micron Technology, Inc.Inventors: Sion C. Quinlan, Bryan Almond, Ken S. Hunt, Andrew M. Lever, Joe A. Ward
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Publication number: 20100009511Abstract: The present invention provides a method and apparatus for a programmable capacitor associated with an input/output pad in the semiconductor device. The apparatus includes a semiconductor die having an upper surface, a first capacitor deployed above the upper surface of the semiconductor die, a separation layer deployed above the first capacitor, and a bond pad deployed above the separation layer such that at least a portion of the bond pad lies above the first capacitor.Type: ApplicationFiled: September 22, 2009Publication date: January 14, 2010Applicant: Micron Technology, Inc.Inventors: Sion C. Quinlan, Bryan Almond, Ken S. Hunt, Andrew M. Lever, Joe A. Ward
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Patent number: 7612701Abstract: A mechanism for discharging parasitic capacitance at an input of an operational amplifier, which is shared between two stages of a pipelined analog-to-digital converter and/or two channels of signal processing circuitry, before the amplifier configuration of the stages/channels is switched. The discharging act occurs when a short reset pulse is generated between two clock phases. The short reset pulse is applied to a switch connected to the operational amplifier input. When the reset pulse closes the switch, a discharge path is created and any parasitic capacitance at the operational amplifier input is discharged through the path. The discharging of the parasitic capacitance substantially mitigates the memory effect and the problems associated with the memory effect.Type: GrantFiled: November 26, 2008Date of Patent: November 3, 2009Assignee: Aptina Imaging CorporationInventors: Taehee Cho, Sandor L. Barna, Andrew M. Lever, Kwang-Bo Cho, Chiajen Lee
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Patent number: 7602039Abstract: The present invention provides a method and apparatus for a programmable capacitor associated with an input/output pad in the semiconductor device. The apparatus includes a semiconductor die having an upper surface, a first capacitor deployed above the upper surface of the semiconductor die, a separation layer deployed above the first capacitor, and a bond pad deployed above the separation layer such that at least a portion of the bond pad lies above the first capacitor.Type: GrantFiled: August 29, 2002Date of Patent: October 13, 2009Assignee: Micron Technology, Inc.Inventors: Sion C. Quinlan, Bryan Almond, Ken S. Hunt, Andrew M. Lever, Joe A. Ward
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Publication number: 20090072899Abstract: A mechanism for discharging parasitic capacitance at an input of an operational amplifier, which is shared between two stages of a pipelined analog-to-digital converter and/or two channels of signal processing circuitry, before the amplifier configuration of the stages/channels is switched. The discharging act occurs when a short reset pulse is generated between two clock phases. The short reset pulse is applied to a switch connected to the operational amplifier input. When the reset pulse closes the switch, a discharge path is created and any parasitic capacitance at the operational amplifier input is discharged through the path. The discharging of the parasitic capacitance substantially mitigates the memory effect and the problems associated with the memory effect.Type: ApplicationFiled: November 26, 2008Publication date: March 19, 2009Inventors: Taehee Cho, Sandor L. Barna, Andrew M. Lever, Kwang-Bo Cho, Chiajen Lee
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Patent number: 7492196Abstract: A fast acting charge pump is provided which is suitable for use in a locked loop circuit where very short duration first and second adjustment pulses are produced by a phase detector. The first complement of the second adjustment pulses are used to switch the output of the charge pump through respective pairs of switching and associated biasing transistors, while a complement of the first and second adjustment pulses are respectively capacitively coupled to interconnection nodes of the pairs of switching and biasing transistors.Type: GrantFiled: March 22, 2005Date of Patent: February 17, 2009Assignee: Micron Technology Inc.Inventor: Andrew M. Lever
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Publication number: 20090043834Abstract: An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random binary sequence generator circuit. The encoded and parallel digital data is coupled through a multiplexer to be serialized in a serializer in a normal mode of operation and the parallel test data is coupled through the multiplexer to be serialized in the serializer in a test mode of operation. Encoded and serial digital data are transmitted to a transmission medium in the normal mode, and serial test data are transmitted to the transmission medium in the test mode. The encoder, the serializer, the sequence generator circuit, and the multiplexer may be fabricated in a single integrated circuit chip. The parallel test data may be parallel pseudo-random binary sequence data. The parallel digital data may include data to generate colors in a visual image.Type: ApplicationFiled: October 6, 2008Publication date: February 12, 2009Inventors: David J. Warner, Ken S. Hunt, Andrew M. Lever
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Patent number: 7471228Abstract: A mechanism for discharging parasitic capacitance at an input of an operational amplifier, which is shared between two stages of a pipelined analog-to-digital converter and/or two channels of signal processing circuitry, before the amplifier configuration of the stages/channels is switched. The discharging act occurs when a short reset pulse is generated between two clock phases. The short reset pulse is applied to a switch connected to the operational amplifier input. When the reset pulse closes the switch, a discharge path is created and any parasitic capacitance at the operational amplifier input is discharged through the path. The discharging of the parasitic capacitance substantially mitigates the memory effect and the problems associated with the memory effect.Type: GrantFiled: November 28, 2006Date of Patent: December 30, 2008Assignee: Micron Technology, Inc.Inventors: Taehee Cho, Sandor L. Barna, Andrew M. Lever, Kwang-Bo Cho, Chiajen Lee
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Patent number: 7441172Abstract: An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random binary sequence generator circuit. The encoded and parallel digital data is coupled through a multiplexer to be serialized in a serializer in a normal mode of operation and the parallel test data is coupled through the multiplexer to be serialized in the serializer in a test mode of operation. Encoded and serial digital data are transmitted to a transmission medium in the normal mode, and serial test data are transmitted to the transmission medium in the test mode. The encoder, the serializer, the sequence generator circuit, and the multiplexer may be fabricated in a single integrated circuit chip. The parallel test data may be parallel pseudo-random binary sequence data. The parallel digital data may include data to generate colors in a visual image.Type: GrantFiled: January 12, 2006Date of Patent: October 21, 2008Assignee: Micron Technology, Inc.Inventors: David J. Warner, Ken S. Hunt, Andrew M. Lever
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Patent number: 7148833Abstract: A mechanism for discharging parasitic capacitance at an input of an operational amplifier, which is shared between two stages of a pipelined analog-to-digital converter and/or two channels of signal processing circuitry, before the amplifier configuration of the stages/channels is switched. The discharging act occurs when a short reset pulse is generated between two clock phases. The short reset pulse is applied to a switch connected to the operational amplifier input. When the reset pulse closes the switch, a discharge path is created and any parasitic capacitance at the operational amplifier input is discharged through the path. The discharging of the parasitic capacitance substantially mitigates the memory effect and the problems associated with the memory effect.Type: GrantFiled: August 26, 2005Date of Patent: December 12, 2006Assignee: Micron Technology, Inc.Inventors: Taehee Cho, Sandor L. Barna, Andrew M. Lever, Kwang-Bo Cho, Chiajen Lee
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Patent number: 7024607Abstract: An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random binary sequence generator circuit. The encoded and parallel digital data is coupled through a multiplexer to be serialized in a serializer in a normal mode of operation and the parallel test data is coupled through the multiplexer to be serialized in the serializer in a test mode of operation. Encoded and serial digital data are transmitted to a transmission medium in the normal mode, and serial test data are transmitted to the transmission medium in the test mode. The encoder, the serializer, the sequence generator circuit, and the multiplexer may be fabricated in a single integrated circuit chip. The parallel test data may be parallel pseudo-random binary sequence data. The parallel digital data may include data to generate colors in a visual image.Type: GrantFiled: June 4, 2002Date of Patent: April 4, 2006Assignee: Micron Technology, Inc.Inventors: David J. Warner, Ken S. Hunt, Andrew M. Lever
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Patent number: 6891411Abstract: A fast acting charge pump is provided which is suitable for use in a locked loop circuit where very short duration first and second adjustment pulses are produced by a phase detector. The first complement of the second adjustment pulses are used to switch the output of the charge pump through respective pairs of switching and associated biasing transistors, while a complement of the first and second adjustment pulses are respectively capacitively coupled to interconnection nodes of the pairs of switching and biasing transistors.Type: GrantFiled: March 29, 2001Date of Patent: May 10, 2005Assignee: Micron Technology, Inc.Inventor: Andrew M. Lever
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Publication number: 20040041245Abstract: The present invention provides a method and apparatus for a programmable capacitor associated with an input/output pad in the semiconductor device. The apparatus includes a semiconductor die having an upper surface, a first capacitor deployed above the upper surface of the semiconductor die, a separation layer deployed above the first capacitor, and a bond pad deployed above the separation layer such that at least a portion of the bond pad lies above the first capacitor.Type: ApplicationFiled: August 29, 2002Publication date: March 4, 2004Applicant: Micron Technology, Inc.Inventors: Sion C. Quinlan, Bryan Almond, Ken S. Hunt, Andrew M. Lever, Joe A. Ward
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Patent number: 6657917Abstract: A phase locked loop system for use with a synchronous dynamic random access memory (SDRAM) or a multi-rate high speed serial transmission buffer is disclosed. The invention includes a phased lock loop having a control voltage for controlling a voltage-controlled oscillator (VCO) that is adjusted, based upon whether the control voltage is within a specific voltage range and whether the VCO frequency is within a specific frequency range. If the control voltage is greater than a voltage maximum and the frequency is not beyond a frequency maximum, the VCO sensitivity is increased. If the control voltage is less than a voltage minimum and the frequency is not below a frequency minimum, the VCO sensitivity is decreased. This ensures that any signal noise or jitter does not have a proportionately large portion of the signal, and therefore minimizes its effect.Type: GrantFiled: July 2, 2001Date of Patent: December 2, 2003Assignee: Micron Technology, Inc.Inventor: Andrew M. Lever
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Publication number: 20030145258Abstract: An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random binary sequence generator circuit. The encoded and parallel digital data is coupled through a multiplexer to be serialized in a serializer in a normal mode of operation and the parallel test data is coupled through the multiplexer to be serialized in the serializer in a test mode of operation. Encoded and serial digital data are transmitted to a transmission medium in the normal mode, and serial test data are transmitted to the transmission medium in the test mode. The encoder, the serializer, the sequence generator circuit, and the multiplexer may be fabricated in a single integrated circuit chip. The parallel test data may be parallel pseudo-random binary sequence data. The parallel digital data may include data to generate colors in a visual image.Type: ApplicationFiled: June 4, 2002Publication date: July 31, 2003Applicant: Micron Technology, Inc.Inventors: David J. Warner, Ken S. Hunt, Andrew M. Lever