Abstract: A method of making the circuitized substrate. The circuitized substrate includes a substrate having a substantially planar upper surface and a conductive layer positioned on the substantially planar upper surface. The conductive layer includes at least one side wall therein, defining an opening in the conductive layer. The conductive layer includes an end portion spaced from the opening, the end portion forming an acute angle with the substantially planar upper surface of the substrate. The at least one side wall is substantially perpendicular to the substantially planar upper surface of the substrate.

Abstract: A method of making a circuitized substrate. A conductive layer having a substantially planar upper surface is formed on and in direct mechanical contact with an upper surface of a substrate. A portion of the conductive layer is removed to form an interim side wall in the conductive layer. A layer of patternable material is formed on the substantially planar upper surface and on the interim side wall. A portion of the layer of patternable material on the conductive layer is removed to expose the interim side wall. A portion of the substantially planar upper surface is removed to form a side wall in the layer of patternable material. Portions of the interim side wall in the conductive layer are removed to form a second side wall and a bottom wall defined by the upper surface of the substrate. The second side wall is substantially perpendicular to the bottom wall.

Abstract: A circuitized substrate and a method of making the circuitized substrate is provided. The circuitized substrate includes a substrate having a substantially planar upper surface and a conductive layer positioned on the substantially planar upper surface. The conductive layer includes at least one side wall therein, defining an opening in the conductive layer. The conductive layer includes an end portion spaced from the opening, the end portion forming an acute angle with the substantially planar upper surface of the substrate. The at least one side wall is substantially perpendicular to the substantially planar upper surface of the substrate.

Abstract: A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.

Abstract: A circuitized substrate and a method of making the circuitized substrate is provided. The circuitized substrate includes a substrate having a substantially planar upper surface and a conductive layer positioned on the substantially planar upper surface. The conductive layer includes at least one side wall therein, defining an opening in the conductive layer. The conductive layer includes an end portion spaced from the opening, the end portion forming an acute angle with the substantially planar upper surface of the substrate. The at least one side wall is substantially perpendicular to the substantially planar upper surface of the substrate.

Abstract: A circuitized substrate and a method of making the circuitized substrate is provided. The circuitized substrate includes a substrate having a substantially planar upper surface and a conductive layer positioned on the substantially planar upper surface. The conductive layer includes at least one side wall therein, defining an opening in the conductive layer. The conductive layer includes an end portion spaced from the opening, the end portion forming an acute angle with the substantially planar upper surface of the substrate. The at least one side wall is substantially perpendicular to the substantially planar upper surface of the substrate.

Abstract: A circuitized substrate and a method of making the circuitized substrate is provided. The circuitized substrate includes a substrate having a substantially planar upper surface and a conductive layer positioned on the substantially planar upper surface. The conductive layer includes at least one side wall therein, defining an opening in the conductive layer. The conductive layer includes an end portion spaced from the opening, the end portion forming an acute angle with the substantially planar upper surface of the substrate. The at least one side wall is substantially perpendicular to the substantially planar upper surface of the substrate.

Abstract: A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.

Abstract: A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.

Abstract: A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.

Abstract: A wiring board for mounting an electrical device, which has an array of connectors thereon arranged in a grid pattern, wherein the connectors have at least two levels of criticality of connection to the substrate. The substrate has a plurality of mounting structure or features arranged in the same grid pattern to connect with the array of connectors on the electrical device. The mounting structures or features are divided into a plurality of at least two groups, with each group corresponding to a level of criticality of the connectors on the device. Each group of mounting structures has a discernible feature differing from each other group, to thereby permit different levels of inspection criteria for each group.

Abstract: Circuit boards or cards containing metallic layers on opposite major surfaces of a dielectric substrate whereby electrical and/or thermal interconnection between the metallic layers is provided in vias that extend through one of the metallic layers, and the dielectric substrate and into the other metallic layer.