Patents by Inventor Andrew M. Waite
Andrew M. Waite has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10896855Abstract: Disclosed are methods for forming a semiconductor device. In some embodiments, a method may include providing a gate structure atop a substrate, providing a gate spacer along a sidewall of the gate structure, and performing a first ion implant to the gate structure and the gate spacer, the first ion implant comprising a thermal implant disposed at a first non-zero angle of inclination with respect to a perpendicular to a plane of the substrate. The method may further include performing a second ion implant to the gate structure and the gate spacer, the second ion implant including a room-temperature ion implant disposed at a second non-zero angle of inclination with respect to the perpendicular to the plane of the substrate, and etching the gate structure and the gate spacer to remove just the second section of the gate spacer.Type: GrantFiled: June 10, 2019Date of Patent: January 19, 2021Assignee: APPLIED Materials, Inc.Inventor: Andrew M. Waite
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Publication number: 20200388541Abstract: Disclosed are methods for forming a semiconductor device. In some embodiments, a method may include providing a gate structure atop a substrate, providing a gate spacer along a sidewall of the gate structure, and performing a first ion implant to the gate structure and the gate spacer, the first ion implant comprising a thermal implant disposed at a first non-zero angle of inclination with respect to a perpendicular to a plane of the substrate. The method may further include performing a second ion implant to the gate structure and the gate spacer, the second ion implant including a room-temperature ion implant disposed at a second non-zero angle of inclination with respect to the perpendicular to the plane of the substrate, and etching the gate structure and the gate spacer to remove just the second section of the gate spacer.Type: ApplicationFiled: June 10, 2019Publication date: December 10, 2020Applicant: APPLIED Materials, Inc.Inventor: Andrew M. Waite
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Patent number: 10600675Abstract: A method may include providing a silicon-on-insulator (SOI) substrate, the SOI substrate comprising an insulator layer and a silicon layer. The silicon layer may be disposed on the insulator layer, where the silicon layer comprises a first silicon thickness variation. The method may include forming an oxide layer on the silicon layer, where the oxide layer has a uniform thickness. The method may include selectively etching the oxide layer on the silicon layer, wherein the oxide layer comprises a first non-uniform oxide thickness. After thermal processing of the SOI substrate in an oxygen ambient, the non-uniform oxide thickness may be configured to generate a second silicon thickness variation in the silicon layer, less than the first silicon thickness variation.Type: GrantFiled: October 9, 2017Date of Patent: March 24, 2020Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Andrew M. Waite, Morgan D. Evans, John Hautala
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Patent number: 10332748Abstract: As etching processes become more aggressive, increased etch resistivity of the hard mask is desirable. Methods of modulating the etch rate of the mask and optionally the underlying material are disclosed. An etch rate modifying species is implanted into the hard mask after the mask etching process is completed. This etch rate modifying species increases the difference between the etch rate of the mask and the etch rate of the underlying material to help preserve the integrity of the mask during a subsequent etching process. In some embodiments, the etch rate of the mask is decreased by the etch rate modifying species. In certain embodiments, the etch rate of the underlying material is increased by the etch rate modifying species.Type: GrantFiled: February 21, 2018Date of Patent: June 25, 2019Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Rajesh Prasad, Steven Robert Sherman, Andrew M. Waite, Sungho Jo, Kyu-Ha Shim, Guy Oteri, Somchintana Norasetthekul
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Publication number: 20190027396Abstract: A method may include providing a silicon-on-insulator (SOI) substrate, the SOI substrate comprising an insulator layer and a silicon layer. The silicon layer may be disposed on the insulator layer, where the silicon layer comprises a first silicon thickness variation. The method may include forming an oxide layer on the silicon layer, where the oxide layer has a uniform thickness. The method may include selectively etching the oxide layer on the silicon layer, wherein the oxide layer comprises a first non-uniform oxide thickness. After thermal processing of the SOI substrate in an oxygen ambient, the non-uniform oxide thickness may be configured to generate a second silicon thickness variation in the silicon layer, less than the first silicon thickness variation.Type: ApplicationFiled: October 9, 2017Publication date: January 24, 2019Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Andrew M. Waite, Morgan D. Evans, John Hautala
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Publication number: 20180182636Abstract: As etching processes become more aggressive, increased etch resistivity of the hard mask is desirable. Methods of modulating the etch rate of the mask and optionally the underlying material are disclosed. An etch rate modifying species is implanted into the hard mask after the mask etching process is completed. This etch rate modifying species increases the difference between the etch rate of the mask and the etch rate of the underlying material to help preserve the integrity of the mask during a subsequent etching process. In some embodiments, the etch rate of the mask is decreased by the etch rate modifying species. In certain embodiments, the etch rate of the underlying material is increased by the etch rate modifying species.Type: ApplicationFiled: February 21, 2018Publication date: June 28, 2018Inventors: Rajesh Prasad, Steven Robert Sherman, Andrew M. Waite, Sungho Jo, Kyu-Ha Shim, Guy Oteri, Somchintana Norasetthekul
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Patent number: 9934982Abstract: As etching processes become more aggressive, increased etch resistivity of the hard mask is desirable. Methods of modulating the etch rate of the mask and optionally the underlying material are disclosed. An etch rate modifying species is implanted into the hard mask after the mask etching process is completed. This etch rate modifying species increases the difference between the etch rate of the mask and the etch rate of the underlying material to help preserve the integrity of the mask during a subsequent etching process. In some embodiments, the etch rate of the mask is decreased by the etch rate modifying species. In certain embodiments, the etch rate of the underlying material is increased by the etch rate modifying species.Type: GrantFiled: December 21, 2015Date of Patent: April 3, 2018Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Rajesh Prasad, Steven Robert Sherman, Andrew M. Waite, Sungho Jo, Kyu-Ha Shim, Guy Oteri, Somchintana Norasetthekul
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Publication number: 20170178914Abstract: As etching processes become more aggressive, increased etch resistivity of the hard mask is desirable. Methods of modulating the etch rate of the mask and optionally the underlying material are disclosed. An etch rate modifying species is implanted into the hard mask after the mask etching process is completed. This etch rate modifying species increases the difference between the etch rate of the mask and the etch rate of the underlying material to help preserve the integrity of the mask during a subsequent etching process. In some embodiments, the etch rate of the mask is decreased by the etch rate modifying species. In certain embodiments, the etch rate of the underlying material is increased by the etch rate modifying species.Type: ApplicationFiled: December 21, 2015Publication date: June 22, 2017Inventors: Rajesh Prasad, Steven Robert Sherman, Andrew M. Waite, Sungho Jo, Kyu-Ha Shim, Guy Oteri, Somchintana Norasetthekul
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Patent number: 9679776Abstract: A method for the selective implantation of a workpiece is disclosed. In place of conventional photoresist, a two layer structure is used. The first layer, referred to as the protective layer, is applied directly to the workpiece and protects the workpiece from harmful etching processes. Additionally, the protective layer has limited ability to stop ions from impacting the workpiece. The second layer, referred to as the blocking layer, which is formed on a portion of the protective layer, is used to block ions from impacting the underlying workpiece. Advantageously, the blocking layer may be selectively etched without affecting the protective layer. Additionally, the protective layer can be removed without affecting the underlying workpiece. Through the use of this two layer technique, high temperature selective implants may be performed on a variety of different semiconductor devices.Type: GrantFiled: July 23, 2015Date of Patent: June 13, 2017Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Andrew M. Waite, Naushad Variam
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Publication number: 20170025277Abstract: A method for the selective implantation of a workpiece is disclosed. In place of conventional photoresist, a two layer structure is used. The first layer, referred to as the protective layer, is applied directly to the workpiece and protects the workpiece from harmful etching processes. Additionally, the protective layer has limited ability to stop ions from impacting the workpiece. The second layer, referred to as the blocking layer, which is formed on a portion of the protective layer, is used to block ions from impacting the underlying workpiece. Advantageously, the blocking layer may be selectively etched without affecting the protective layer. Additionally, the protective layer can be removed without affecting the underlying workpiece. Through the use of this two layer technique, high temperature selective implants may be performed on a variety of different semiconductor devices.Type: ApplicationFiled: July 23, 2015Publication date: January 26, 2017Inventors: Andrew M. Waite, Naushad Variam
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Patent number: 9299564Abstract: Various methods for implanting dopant ions into a three dimensional feature of a semiconductor wafer are disclosed. The implant temperature may be varied to insure that the three dimensional feature, after implant, has a crystalline inner core, which is surrounded by an amorphized surface layer. The crystalline core provides a template from which the crystalline structure for the rest of the feature can be regrown. In some embodiments, the implant energy and the implant temperature may each be modified to achieve the desired crystalline inner core with the surrounding amorphized surface layer.Type: GrantFiled: May 20, 2013Date of Patent: March 29, 2016Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Andrew M. Waite, Stanislav S. Todorov
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Publication number: 20150214339Abstract: A method to process a semiconductor device includes performing a first ion implant comprising first ions into a thin crystalline semiconductor structure, the first ion dose amorphizing a first region of the thin crystalline semiconductor structure; performing a second ion implant comprising dopant ions of a dopant species into at least the first region of the thin crystalline semiconductor structure; and performing at least one anneal of the semiconductor device after the first implant, wherein after the first and second implant and the at least one anneal, the thin crystalline semiconductor structure forms a mono-crystalline region without defects.Type: ApplicationFiled: January 24, 2014Publication date: July 30, 2015Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: ANDREW M. WAITE, KALIPATNAM VIVEK RAO
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Patent number: 9018064Abstract: A method of doping the polycrystalline channel in a vertical FLASH device is disclosed. This method uses a plurality of high energy ion implants to dope the channel at various depths of the channel. In some embodiments, these ion implants are performed at an angle offset from the normal direction, such that the implanted ions pass through at least a portion of the surrounding ONO stack. By passing through the ONO stack, the distribution of ranges reached by each ion may differ from that created by a vertical implant.Type: GrantFiled: July 10, 2013Date of Patent: April 28, 2015Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Andrew M. Waite, Jonathan Gerald England, Rajesh Prasad
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Publication number: 20150062772Abstract: An electrostatic chuck for implanting ions at high temperatures is disclosed. The electrostatic chuck includes an insulating base, with electrically conductive electrodes disposed thereon. A dielectric top layer is disposed on the electrodes. A barrier layer is disposed on the dielectric top layer so as to be between the dielectric top layer and the workpiece. This barrier layer serves to inhibit the migration of particles from the dielectric top layer to the workpiece, which is clamped on the chuck. In some embodiments, a protective layer is applied on top of the barrier layer to prevent abrasion.Type: ApplicationFiled: August 27, 2013Publication date: March 5, 2015Inventors: Andrew M. Waite, James Carroll
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Publication number: 20150017772Abstract: A method of doping the polycrystalline channel in a vertical FLASH device is disclosed. This method uses a plurality of high energy ion implants to dope the channel at various depths of the channel. In some embodiments, these ion implants are performed at an angle offset from the normal direction, such that the implanted ions pass through at least a portion of the surrounding ONO stack. By passing through the ONO stack, the distribution of ranges reached by each ion may differ from that created by a vertical implant.Type: ApplicationFiled: July 10, 2013Publication date: January 15, 2015Inventors: Andrew M. Waite, Jonathan Gerald England, Rajesh Prasad
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Patent number: 8846508Abstract: Methods to implant ions into the sidewall of a three dimensional high aspect ratio feature, such as a trench or via, are disclosed. The methods utilize a phenomenon known as knock-in, which causes a first species of ions, already disposed in the fill material, to become implanted in the sidewall when these ions are struck by ions of a second species being implanted into the fill material. In some embodiments, these first species and second species have similar masses to facilitate knock-in. In some embodiments, the entire hole is not completely filled with fill material. Rather, some fill material is deposited, an ion implant is performed to cause knock-in to the sidewall adjacent to the deposited fill material, and the process is repeated until the hole is filled.Type: GrantFiled: July 15, 2013Date of Patent: September 30, 2014Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Jonathan Gerald England, Andrew M. Waite, Simon Ruffell
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Publication number: 20140162435Abstract: Various methods for implanting dopant ions into a three dimensional feature of a semiconductor wafer are disclosed. The implant temperature may be varied to insure that the three dimensional feature, after implant, has a crystalline inner core, which is surrounded by an amorphized surface layer. The crystalline core provides a template from which the crystalline structure for the rest of the feature can be regrown. In some embodiments, the implant energy and the implant temperature may each be modified to achieve the desired crystalline inner core with the surrounding amorphized surface layer.Type: ApplicationFiled: May 20, 2013Publication date: June 12, 2014Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Andrew M. Waite, Stanislav S. Todorov
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Patent number: 8193592Abstract: A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with respect to the gate structure. An ion implantation process is performed at a non-zero tilt angle. At least one spacer and the gate electrode mask a portion of the surface during the ion implantation process such that the source extension and drain extension are asymmetrically positioned with respect to the gate structure by an asymmetry measure.Type: GrantFiled: October 14, 2010Date of Patent: June 5, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Frank Bin Yang, Andrew M. Waite, Scott Luning
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Patent number: 8148214Abstract: A stressed field effect transistor and methods for its fabrication are provided. The field effect transistor comprises a silicon substrate with a gate insulator overlying the silicon substrate. A gate electrode overlies the gate insulator and defines a channel region in the silicon substrate underlying the gate electrode. A first silicon germanium region having a first thickness is embedded in the silicon substrate and contacts the channel region. A second silicon germanium region having a second thickness greater than the first thickness and spaced apart from the channel region is also embedded in the silicon substrate.Type: GrantFiled: January 28, 2009Date of Patent: April 3, 2012Assignee: GlobalFoundries Inc.Inventors: Andrew M. Waite, Scott Luning
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Patent number: 8124473Abstract: A strain enhanced semiconductor device and methods for its fabrication are provided. One method comprises embedding a strain inducing semiconductor material in the source and drain regions of the device to induce a strain in the device channel. Thin metal silicide contacts are formed to the source and drain regions so as not to relieve the induced strain. A layer of conductive material is selectively deposited in contact with the thin metal silicide contacts, and metallized contacts are formed to the conductive material.Type: GrantFiled: April 12, 2007Date of Patent: February 28, 2012Assignee: Advanced Micro Devices, Inc.Inventors: James N. Pan, Sey-Ping Sun, Andrew M. Waite