Patents by Inventor Andrew M. Welin

Andrew M. Welin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SYSTEMS, PROCESSES AND INTEGRATED CIRCUITS FOR IMPROVED PACKET SCHEDULING OF MEDIA OVER PACKET
    Publication number: 20100118819
    Abstract: A method of processing first and second record packets of real-time information includes computing for each packet a deadline interval and ordering processing of the packets according to the respective deadline intervals. A single-chip integrated circuit has a processor circuit and embedded electronic instructions forming an egress packet control establishing an egress scheduling list structure and operations in the processor circuit that extract a packet deadline intervals, place packets in the egress scheduling list according to deadline intervals; and embed a decoder that decodes the packets according to a priority depending to their deadline intervals.
    Type: Application
    Filed: January 18, 2010
    Publication date: May 13, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Andrew M. Welin
  • Processing packets based on deadline intervals
    Patent number: 6975629
    Abstract: A method of processing first and second record packets of real-time information includes computing for each packet a deadline interval and ordering processing of the packets according to the respective deadline intervals. A single-chip integrated circuit has a processor circuit and embedded electronic instructions forming an egress packet control establishing an egress scheduling list structure and operations in the processor circuit that extract a packet deadline intervals, place packets in the egress scheduling list according to deadline intervals; and embed a decoder that decodes the packets according to a priority depending to their deadline intervals.
    Type: Grant
    Filed: February 16, 2001
    Date of Patent: December 13, 2005
    Assignee: Texas Instruments Incorporated
    Inventor: Andrew M. Welin
  • Systems, processes and integrated circuits for improved packet scheduling of media over packet
    Publication number: 20020031086
    Abstract: A method of processing first and second record packets of real-time information includes computing for each packet a deadline interval and ordering processing of the packets according to the respective deadline intervals. A single-chip integrated circuit has a processor circuit and embedded electronic instructions forming an egress packet control establishing an egress scheduling list structure and operations in the processor circuit that extract a packet deadline intervals, place packets in the egress scheduling list according to deadline intervals; and embed a decoder that decodes the packets according to a priority depending to their deadline intervals.
    Type: Application
    Filed: February 16, 2001
    Publication date: March 14, 2002
    Inventor: Andrew M. Welin
  • Inherently micro programmable high level language processor
    Patent number: 3938103
    Abstract: An inherently micro programmable high level language processor and a micro programming language which permits the micro programmer to program in terms of constructs related to the process of interpretation is disclosed. Such constructs include, but are not limited to, character extraction and stack manipulation. A method of interpretation which embodies the methods of sequential extraction and linear decoding at the micro programming level is also presented.
    Type: Grant
    Filed: March 20, 1974
    Date of Patent: February 10, 1976
    Inventor: Andrew M. Welin