Abstract: The signal sensed on a heart pacer electrode is converted by a delta modulator to a sequence of samples of 0 and 1 bit values. The resulting bit sequence is delayed, and the original bit sequence and its delayed version are continuously subtracted from each other in a clocked up/down counter to derive a count. When the count reaches a threshold value, three different recognition logic circuits are triggered and they then operate for two milliseconds. One circuit recognizes a beat if the count does not drop below another, lower threshold value during the timing interval. A second circuit detects a beat if the count remains above the threshold level for at least 50% of the time during the timing interval. The third circuit detects a beat by operating directly on the delta modulator output bit sequence; it checks whether bits of the value indicative of the triggering event predominate over bits of the opposite value during the timing interval.