Patents by Inventor Andrew Mark Greene

Andrew Mark Greene has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit having oxidized gate cut region and method to fabricate same
    Patent number: 10128238
    Abstract: A method includes epitaxially depositing source/drains on parallel semiconductor fins having parallel polysilicon gate precursor structures disposed thereon orthogonally to the fins, where two adjacent polysilicon gate precursor structures are joined together and connected at ends thereof by a polysilicon loop portion. The method further includes oxidizing the ends of the polysilicon precursor gate structures, the connecting polysilicon loop portion and any semiconductor nodules that formed on the connecting polysilicon loop portion during the step of epitaxially depositing the source/drains. A structure includes a substrate; a plurality of parallel semiconductor fins disposed on the substrate; a plurality of parallel metal gate structures overlying the plurality of fins and orthogonal to the plurality of fins; and a plurality of source/drain structures disposed on the fins.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: November 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Andrew Mark Greene, Peng Xu
  • INTEGRATED CIRCUIT HAVING OXIDIZED GATE CUT REGION AND METHOD TO FABRICATE SAME
    Publication number: 20180047726
    Abstract: A method includes epitaxially depositing source/drains on parallel semiconductor fins having parallel polysilicon gate precursor structures disposed thereon orthogonally to the fins, where two adjacent polysilicon gate precursor structures are joined together and connected at ends thereof by a polysilicon loop portion. The method further includes oxidizing the ends of the polysilicon precursor gate structures, the connecting polysilicon loop portion and any semiconductor nodules that formed on the connecting polysilicon loop portion during the step of epitaxially depositing the source/drains. A structure includes a substrate; a plurality of parallel semiconductor fins disposed on the substrate; a plurality of parallel metal gate structures overlying the plurality of fins and orthogonal to the plurality of fins; and a plurality of source/drain structures disposed on the fins.
    Type: Application
    Filed: August 9, 2016
    Publication date: February 15, 2018
    Inventors: Kangguo Cheng, Andrew Mark Greene, Peng Xu