Abstract: Verification tests perform hardware and software co-verification on a system under verification. Each signal interface controller coupled to the system performs a test action transferring at least one of stimulus signals and response signals between a corresponding portion of the system under verification and the signal interface controller during verification. A debugger controls an associated processing unit that executes software routines. A debugger signal interface controller performs test actions transferring stimulus signals and response signals between the debugger and the debugger signal interface controller during verification. A test manager transfers test controlling messages to these interface controllers identifying the test actions to be performed. As a result, the test manager controls the processing unit via the debugger signal interface controller and the debugger in order to coordinate the execution of the software routines with a sequence of verification tests.

Abstract: An apparatus and method are provided for performing a sequence of verification tests to verify the design of a data processing system. The apparatus comprises a system under verification representing the design of the data processing system, the system under verification including a component model representing at least one hardware component of the data processing system. The component model includes an interface module through which the component model interacts with other portions of the system under verification during performance of the verification tests. An alternative model is provided for representing the hardware component for selected verification tests, and the interface module comprises a verification interface module which is responsive to switch criteria specified by the alternative model to switch in the alternative model in place of the component model.

Abstract: A test system for data processing circuit design emulates multiple bus masters and provides an arbitration mechanism for coordinating arbitration between those bus masters in the design emulation. The shared bus being tested may be a multi-layer bus and one or more of the bus masters being emulated or bus slaves being emulated may be cut-down emulations modelling the bus interaction itself or full emulations of the intended bus master circuit or bus slave circuit including its operational data processing.

Abstract: Simulation of the operation of a data processing apparatus having a number of master logic units and slave logic units coupled via a bus is provided. The data processing apparatus performs data transfers between the master logic units and the slave logic units over the bus. Anticipated timing information for each successive data transfer over the bus is generated by assuming that each successive data transfer can occur with exclusive access to the bus, determining whether the anticipated timing information indicates that two or more concurrent data transfers would occur on the bus, and in the event that the anticipated timing information indicates that two or more concurrent data transfers would occur on the bus, generating revised timing information for those data transfers, the revised timing information being generated using bus status information until those data transfers have been completed.

Abstract: A hardware simulation and validation system is provided using a plurality of signal interface controllers to exchange stimulus and response signals with a hardware simulation. The action of the signal interface controllers is coordinated by a test scenario manager which exchanges test scenario controlling messages with the signal interface controllers. The test scenario controlling messages specify simulation actions to be performed and when those simulation actions are to be performed.

Abstract: A method of generating a configuration of an integrated circuit 2 having an interconnect component 14 connecting a plurality of devices 4, 6, 8, 10, 12 uses selecting a device to be connected to the interconnect component, reading interface parameters of that device from a file or model (e.g. IP-XACT), selecting parameters of an interface “if” of the interconnect component to match the read parameters, detecting and making any settings in the configuration of the interconnect component 14 itself required to match the selected parameters of the interface and then detecting any changes required in the configuration of any devices previously connected to the interconnect component required to match the configuration of the interconnect component as it now stands. In this way, configuration of the interconnect component can be at least semi-automated with a reduction in the possibility of errors and an increase in the speed of such configuration.

Abstract: An apparatus and method are provided for performing a sequence of verification tests to verify the design of a data processing system. The apparatus comprises a system under verification representing the design of the data processing system, the system under verification including a component model representing at least one hardware component of the data processing system. The component model includes an interface module through which the component model interacts with other portions of the system under verification during performance of the verification tests. An alternative model is provided for representing the hardware component for selected verification tests, and the interface module comprises a verification interface module which is responsive to switch criteria specified by the alternative model to switch in the alternative model in place of the component model.

Abstract: A verification environment is provided that co-verifies a software component 8 and a hardware component 10. Within the same environment using a common test controller 18 both hardware stimuli and software stimuli may be applied to their respective simulators. The response of both the software and the hardware to the simulation conducted can be monitored to check for proper operation.

Abstract: A simulation system is provided for simulating operation of a plurality of hardware devices in combination with an instruction set simulator simulating execution of program instructions by a program core. A test scenario manager acts as a master and serves to command the hardware devices and the instruction set simulator with stimulus signals to simulate various specified activity.

Abstract: The present invention provides a system and method for testing compliance of a device with a bus protocol. The method comprises the steps of reading a configuration file containing predetermined parameters identifying the type of device and capabilities of the device, and then employing a configuration engine to dynamically generate a test environment for the device by creating selected test components which are coupled via the bus with a representation of the device to form the test environment, the test components being selected dependent on the configuration file. A test sequence is then executed, during which signals passed between the representation of the device and one or more of the test components are monitored to generate result data indicating compliance with the bus protocol. This approach has been found to provide a particularly user friendly and efficient approach for testing compliance of devices with a bus protocol.

Abstract: A test system for data processing circuit design emulates multiple bus masters and provides an arbitration mechanism for coordinating arbitration between those bus masters in the design emulation. The shared bus being tested may be a multi-layer bus and one or more of the bus masters being emulated or bus slaves being emulated may be cut-down emulations modelling the bus interaction itself or full emulations of the intended bus master circuit or bus slave circuit including its operational data processing.

Abstract: A simulation system is provided for simulating operation of a plurality of hardware devices in combination with an instruction set simulator simulating execution of program instructions by a program core. A test scenario manager acts as a master and serves to command the hardware devices and the instruction set simulator with stimulus signals to simulate various specified activity.

Abstract: A hardware simulation and validation system is provided using a plurality of signal interface controllers to exchange stimulus and response signals with a hardware simulation. The action of the signal interface controllers is coordinated by a test scenario manager which exchanges test scenario controlling messages with the signal interface controllers. The test scenario controlling messages specify simulation actions to be performed and when those simulation actions are to be performed.

Abstract: The present invention provides a system and method for testing compliance of a device with a bus protocol. The method comprises the steps of reading a configuration file containing predetermined parameters identifying the type of device and capabilities of the device, and then employing a configuration engine to dynamically generate a test environment for the device by creating selected test components which are coupled via the bus with a representation of the device to form the test environment, the test components being selected dependent on the configuration file. A test sequence is then executed, during which signals passed between the representation of the device and one or more of the test components are monitored to generate result data indicating compliance with the bus protocol. This approach has been found to provide a particularly user friendly and efficient approach for testing compliance of devices with a bus protocol.

Abstract: A verification environment is provided that co-verifies a software component 8 and a hardware component 10. Within the same environment using a common test controller 18 both hardware stimuli and software stimuli may be applied to their respective simulators. The response of both the software and the hardware to the simulation conducted can be monitored to check for proper operation.