Abstract: A computer system that detects for a PCI Express compliant endpoint device is described. Specifically, the computer system clocks transmit and receive circuits at a first frequency and initiates a training sequence. If the endpoint device successfully trains at the first frequency, the endpoint device is PCI Express compliant. Otherwise, the computer system initiates another training sequence at a second frequency.

Abstract: An integrated circuit is disclosed. The integrated circuit includes a power delivery network (PDN), a first voltage rail coupled to the PDN, an input/output (I/O) buffer coupled to the first voltage rail and a driver coupled to the I/O buffer. The driver transmits a current waveform to the I/O buffer whenever a switching event occurs at the I/O buffer.

Abstract: An apparatus and a method for active case cancellation for an inductor/capacitor network have been presented. One embodiment of the method includes generating a derivative of an input to a die from a package, the derivative being out of phase relative to the input. The method further comprises substantially canceling resonance between an inductance of the package and a capacitance of the die with the derivative.

Abstract: In some embodiments, a chip includes first and second nodes, a variable voltage source, and transmitter and control circuitry. The transmitter includes a driver coupled to the first and second nodes, and first and second resistive structures coupled between the first and second nodes, respectively, and the variable voltage source. The control circuitry selects an impedance level for the first and second resistive structures, and detect coupling of a remote receiver to the transmitter through interconnects and detect decoupling of the remote receiver from the transmitter. Other embodiments are described and claimed.

Abstract: A serial point to point link that communicatively couples an integrated circuit (IC) device to another IC device is initialized by transferring a training sequence of symbols over the link. Registers of the IC device are programmed, to set a symbol data pattern and configure a lane transmitter for the link. A start bit in a register of the IC device is programmed, to request that the link be placed in a measurement mode. In this mode, the IC device instructs the other IC device to enter a loopback mode for the link. The IC device transmits a sequence of test symbols over the link and evaluates a loopback version of the sequence for errors. The sequence of test symbols have a data pattern, and are transmitted, as configured by the registers. Other embodiments are also described and claimed.

Abstract: In some embodiments, a chip includes first and second nodes, a variable voltage source, and transmitter and control circuitry. The transmitter includes a driver coupled to the first and second nodes, and first and second resistive structures coupled between the first and second nodes, respectively, and the variable voltage source. The control circuitry selects an impedance level for the first and second resistive structures, and detect coupling of a remote receiver to the transmitter through interconnects and detect decoupling of the remote receiver from the transmitter. Other embodiments are described and claimed.

Abstract: In some embodiments, a chip includes first and second nodes, a variable voltage source, a transmitter, change detection circuitry, and control circuitry. The transmitter includes a driver coupled to the first and second nodes, and first and second resistive structures coupled between the first and second nodes, respectively, and the variable voltage source. The change detection circuitry detects changes in voltages of the first and second nodes following a change in voltage of the variable voltage source. The control circuitry determines whether the changes in voltages of the first and second nodes are consistent with the transmitter being coupled through interconnects to a remote receiver. Other embodiments are described and claimed.

Abstract: An apparatus and a method for active phase cancellation for an inductor/capacitor network have been disclosed. One embodiment of the apparatus includes a package and a die mounted on the package. The die comprises circuitry to to substantially cancel resonance between an inductance of the package and a capacitance of the die.

Abstract: Briefly, system and method for message-based power management which may be used, for example, in computer systems and communications networks. Embodiments of the present invention may include, for example, a device connected to a power management controller (PMC); the device and/or the PMC may send, receive, and/or process power management event (PME) messages. Embodiments of the present invention may operate using links in communicative and/or non-communicative modes. Embodiments of the present invention may include a switch, to send/receive, process, create, re-format and/or route one or more PME message on behalf of various devices, for example, a Peripheral Component Interconnect (PCI) device.

Abstract: A first device and a second device, each coupled to one or more signal paths, attempting to transmit symbols over one or more of the signal paths, identifying one or more signal paths over each of which each device is able to transmit a symbol to the other device and over which each device is able to receive a symbol from the other device, and enrolling the identified signal paths into an aggregation of signal paths operable to provide for communication between the devices.

Abstract: An apparatus includes an input/output (I/O) address verification unit that determines whether an I/O address received from a processor is protected. An interrupt generator is coupled to the I/O address verification unit. The interrupt generator generates an interrupt if the I/O address is protected. An interrupt recorder is coupled to the address verification unit. The interrupt recorder records a cause of the interrupt.

Abstract: An apparatus includes an input/output (I/O) address verification unit that determines whether an I/O address received from a processor is protected. An interrupt generator is coupled to the I/O address verification unit. The interrupt generator generates an interrupt if the I/O address is protected. An interrupt recorder is coupled to the address verification unit. The interrupt recorder records a cause of the interrupt.

Abstract: An apparatus includes an input/output (I/O) address verification unit that determines whether an I/O address received from a processor is protected. An interrupt generator is coupled to the I/O address verification unit. The interrupt generator generates an interrupt if the I/O address is protected. An interrupt recorder is coupled to the address verification unit. The interrupt recorder records a cause of the interrupt.

Abstract: An apparatus includes an input/output (I/O) address verification unit that determines whether an I/O address received from a processor is protected. An interrupt generator is coupled to the I/O address verification unit. The interrupt generator generates an interrupt if the I/O address is protected. An interrupt recorder is coupled to the address verification unit. The interrupt recorder records a cause of the interrupt.

Abstract: A multi-axial position sensor assembly for a joystick in which sensor/magnet pairs are positioned orthogonally on concentric gimbal rings such that each sensor and corresponding magnet pivot in relation to each other as a result of joystick movement. The sensors produce a reference output voltage when the joystick is centered and the sensors are aligned with the magnets. As a magnet rotates in relation to a sensor, the sensor produces an output voltage which is proportional to the angle of rotation and which has a polarity dependent upon the direction of rotation relative to the centered position.