Abstract: Described herein are cannabinoid formulations in combination with curcumin for oral administration. Further described herein are methods for orally administering one or more cannabinoids to a subject in need thereof and manufacturing oral formulations as described herein.

Abstract: A system for estimating an amount of soot in an exhaust particulate filter includes a delta P soot load estimate generator configured to generate a first soot load estimate as a function of a pressure drop and a mass flow of exhaust. The system further includes a model estimate generator configured to generate a second soot load estimate as a function of a modeled engine performance. A trust factor generator is configured to determine a trust factor signal as a function of at least one engine operating characteristic, and a decision generator is configured to determine whether to use the first soot load estimate or the second soot load estimate as a function of the trust factor signal.

Abstract: A system for estimating an amount of soot in an exhaust particulate filter includes a delta P soot load estimate generator configured to generate a first soot load estimate as a function of a pressure drop and a mass flow of exhaust. The system further includes a model estimate generator configured to generate a second soot load estimate as a function of a modeled engine performance. A trust factor generator is configured to determine a trust factor signal as a function of at least one engine operating characteristic, and a decision generator is configured to determine whether to use the first soot load estimate or the second soot load estimate as a function of the trust factor signal.

Abstract: An apparatus including circuitry configured to detect and correct an ECC error in a non-targeted portion of a load access to a first data in a memory. An ECC error check circuit is configured to convey a first indication in response to detecting an error in a non-targeted first portion of the first data. A microcode unit is coupled to receive the first indication that the ECC check circuit has detected the ECC error and in response to the indication dispatch a first microcode routine stored by the microcode unit. The first microcode routine includes instructions which, when executed, correct the ECC error in the first portion. Correction of the error in the first portion does not include cancellation of data corresponding to the load access.

Abstract: A method and apparatus for encoding cache replacement priority information is disclosed. A computer software program may be used to allow programmers to specify which portions of source or object code being generated should be treated as high priority with respect to cache line replacement. The cache line replacement information may be encoded as special prefix bits/bytes, special opcodes, or as a separate data file. The software program may also be configured to autonomously determine which portions of the object code being generated should be identified as high priority with respect to cache line replacement. The program may also allow the programmer to specify certain points in the code after which instructions that had previously been identified as high priority should be reclassified as low priority. Opcodes or prefix bytes clearing previously stored cache replacement information may also be encoded in the object code.

Abstract: A branch prediction unit stores a set of branch prediction history bits and branch selectors corresponding to each of a group of contiguous instruction bytes stored in an instruction cache. While only one bit is used to represent branch prediction history, three distinct states are represented in conjunction with the absence of a branch prediction. This provides for the storage of fewer bits, while maintaining a high degree of branch prediction accuracy. Each branch selector identifies the branch prediction to be selected if a fetch address corresponding to that branch selector is presented. In order to minimize the number of branch selectors stored for a group of contiguous instruction bytes, the group is divided into multiple byte ranges. The largest byte range may include a number of bytes comprising the shortest branch instruction in the instruction set (exclusive of the return instruction). For example, the shortest branch instruction may be two bytes in one embodiment.

Abstract: A microprocessor configured to use historical scan information to speed instruction scanning is disclosed. The microprocessor may comprise an instruction cache, a scanning history table, routing logic, and two or more scanning units. The instruction cache is configured to output sequences of stored instruction bytes in response to receiving corresponding fetch addresses. The scanning history table, which may also receive the fetch addresses, is configured to output corresponding stored scan block boundary information. The routing logic, which is coupled between the instruction cache, scanning history table, and scanning units, is configured to route the first N instructions to the first scanning unit, and the second N instructions to the second scanning unit, wherein N is a predetermined integer greater than one. The scanning units are configured to operate independently and in parallel.

Abstract: An instruction cache employing a cache holding register is provided. When a cache line of instruction bytes is fetched from main memory, the instruction bytes are temporarily stored into the cache holding register as they are received from main memory. The instruction bytes are predecoded as they are received from the main memory. If a predicted-taken branch instruction is encountered, the instruction fetch mechanism within the instruction cache begins fetching instructions from the target instruction path. This fetching may be initiated prior to receiving the complete cache line containing the predicted-taken branch instruction. As long as instruction fetches from the target instruction path continue to hit in the instruction cache, these instructions may be fetched and dispatched into a microprocessor employing the instruction cache. The remaining portion of the cache line of instruction bytes containing the predicted-taken branch instruction is received by the cache holding register.

Abstract: A predecode unit is configured to predecode variable byte-length instructions prior to their storage within an instruction cache of a superscalar microprocessor. The predecode unit generates three predecode bits associated with each byte of instruction code: a "start" bit, an "end" bit, and a "functional" bit. The start bit is set if the associated byte is the first byte of the instruction. Similarly, the end bit is set if the byte is the last byte of the instruction. The functional bits convey information regarding the location of an opcode byte for a particular instruction as well as an indication of whether the instruction can be decoded directly by the decode logic of the processor or whether the instruction is executed by invoking a microcode procedure controlled by an MROM unit. For fast path instructions, the functional bit is set for each prefix byte included in the instruction, and cleared for other bytes.

Abstract: A microprocessor stores cache-line-related data (e.g. branch predictions or predecode data, in the illustrated embodiments) in a storage which includes fewer storage locations than the number of cache lines in the instruction cache. Each storage location in the storage is mappable to multiple cache lines, any one of which can be associated with the data stored in the storage location. The storage may thereby be smaller than a storage which provides an equal number of storage locations as the number of cache lines in the instruction cache. Access time to the storage may be reduced, therefore providing for a higher frequency implementation. Still further, semiconductor substrate area occupied by the storage may be decreased. In one embodiment, the storage is indexed by a subset of the index bits used to index the instruction cache. The subset comprises the least significant bits of the cache index.

Abstract: An instruction cache employing a cache holding register is provided. When a cache line of instruction bytes is fetched from main memory, the instruction bytes are temporarily stored into the cache holding register as they are received from main memory. The instruction bytes are predecoded as they are received from the main memory. If a predicted-taken branch instruction is encountered, the instruction fetch mechanism within the instruction cache begins fetching instructions from the target instruction path. This fetching may be initiated prior to receiving the complete cache line containing the predicted-taken branch instruction. As long as instruction fetches from the target instruction path continue to hit in the instruction cache, these instructions may be fetched and dispatched into a microprocessor employing the instruction cache. The remaining portion of the cache line of instruction bytes containing the predicted-taken branch instruction is received by the cache holding register.

Abstract: A branch prediction unit includes a branch prediction entry corresponding to a group of contiguous instruction bytes. The branch prediction entry stores branch predictions corresponding to branch instructions within the group of contiguous instruction bytes. Additionally, the branch prediction entry stores a set of branch selectors corresponding to the group of contiguous instruction bytes. The branch selectors identify which branch prediction is to be selected if the corresponding byte (or bytes) is selected by the offset portion of the fetch address. Still further, a predicted branch selector is stored. The predicted branch selector is used to select a branch prediction for forming the fetch address. In parallel, a selected branch selector is selected from the set of branch selectors. The predicted branch selector is verified using the selected branch selector.

Abstract: A memory including first storage circuits for storing first values and second storages circuit for storing second values is provided. The first value may be retired branch prediction information, while the second value may be speculative branch prediction information. The speculative branch prediction information is updated when the corresponding instructions are fetched, and the retired branch prediction value is updated when the corresponding branch instruction is retired. The speculative branch prediction information is used to form branch predictions. Therefore, the speculatively fetched and executed branches influence subsequent branch predictions. Upon detection of a mispredicted branch or an instruction which causes an exception, the speculative branch prediction information is updated to the corresponding retired branch prediction information. An update circuit is coupled between the first and second storage circuits for transmitting the updated information upon assertion of a control signal.

Abstract: An apparatus for managing system interrupt operations in a computing system including a processing unit and peripheral devices. The apparatus comprises a transmission circuit for transmitting signals which effects operative connection among the peripheral devices and the processing unit; an interrupt drive circuit for generating interrupt signals associated with each peripheral device drives the transmission circuit from a first signal level to a second signal level to effect generating an interrupt signal; and an acknowledge drive circuit for generating an acknowledge signal by the processing unit. Each acknowledge drive circuit drives the transmission circuit from an initial signal level to an indicating signal level to effect generation of an acknowledge signal, and drives the transmission circuit from the indicating signal level to the initial signal level upon termination of the acknowledge signal.

Abstract: An apparatus for managing communication within a computing system which includes a processing unit and a plurality of peripheral units. The processing unit receives information from a plurality of loci within the computing system and determines an enablement profile in response to such information according to predetermined criteria. The processing unit responds to the enablement profile to selectively enable specified peripheral units. The apparatus comprises a monitoring circuit for monitoring the enablement profile; a logic circuit for logically treating the enablement profile and generating a feedback signal representative of the enablement profile; and a transmission circuit for communicating the feedback signal from the logic circuit to the processing unit. The processing unit responds to the feedback signal to determine whether to employ a transfer trapping discipline whereby transfers destined for a non-enabled peripheral unit are stored until the non-enabled unit is enabled.