Abstract: A method for cleaning a casing of an oil well is disclosed. Operational parameters for a cleaning tool may be defined based, at least in part, on results of a survey of the well. The cleaning tool may include a discharge head to generate electrical discharges between a pair of electrodes, the electrical discharges causing shock waves to remove deposits from the casing. The cleaning tool may be lowered into the casing. The cleaning tool may generate shock waves in accordance with the defined operational parameters to clean a predetermined target portion of the casing. The cleaning tool may be withdrawn from the casing.

Abstract: A tool for cleaning a casing of an oil well may include an elongate housing configured to be lowered into a well casing. A discharge head may be disposed at one end of the housing, the discharge head including a first electrode having a first end surface, a first insulator surrounding the first electrode, a surface of the first insulator substantially flush with the first end surface, and a second electrode having a second end surface separated from the first end surface by a discharge gap. An energy reservoir and a switch may be disposed within the housing, the switch configured to selectively couple the energy reservoir to the first electrode and the second electrode to cause energy stored in the energy reservoir to discharge across the discharge gap.

Abstract: A method for cleaning a casing of an oil well is disclosed. Operational parameters for a cleaning tool may be defined based, at least in part, on results of a survey of the well. The cleaning tool may include a discharge head to generate electrical discharges between a pair of electrodes, the electrical discharges causing shock waves to remove deposits from the casing. The cleaning tool may be lowered into the casing. The cleaning tool may generate shock waves in accordance with the defined operational parameters to clean a predetermined target portion of the casing. The cleaning tool may be withdrawn from the casing.

Abstract: A wrench for handling a fastener, involving an elongated member with a proximal end and a distal end, a step pad being disposed proximate the elongated member proximal end and for providing additional torque, and an adapter being disposed proximate the elongated member distal end. The adapter may include an element, such as a socket member and a ratchet member. The elongated member distal end may include a tool member.

Abstract: A wrench for handling a fastener, involving an elongated member with a proximal end and a distal end, a step pad being disposed proximate the elongated member proximal end and for providing additional torque, and an adapter being disposed proximate the elongated member distal end. The adapter may include an element, such as a socket member and a ratchet member. The elongated member distal end may include a tool member.

Abstract: A method of providing synchronization of the clocks of all of the media gateways of an Ethernet, or equivalent, IP network used in the transmission of audio data between media gateways using a clock provided by the PSTN. The selection of one of the media gateways connected to the PSTN, termed the master CoHub (Central Office Hub), is used as a clock master. This CoHub derives its clock from its TDM-interface's frame-synchronization with the PSTN to which it is connected. Utilizing this gateway-synchronization method, all MG's are synchronized to this PSTN clock-source.

Abstract: An AC waveform monitoring system includes detecting circuitry for providing a sensed analog signal. Oscillator circuitry is coupled to the detecting circuitry for providing a zero crossing signal. The oscillator circuitry is synchronized with a frequency of the sensed analog signal. Signal processing circuitry is coupled to both the detecting circuitry and the oscillator circuitry for identifying a peak voltage signal and an integral volt-seconds signal of the sensed analog signal responsive to the zero crossing signal. Digital processing circuitry is coupled to the signal processing circuitry and the oscillator circuitry. The digital processing circuitry includes memory for storing a plurality of predetermined signal voltage boundary values and a program utilizing the identified peak voltage signal, the integral volt-seconds signal and the stored predetermined signal values to identify an abnormal voltage event.

Abstract: A line noise signal measurement system is provided with detecting circuitry for providing a sensed analog signal. Compression circuitry is coupled to the detecting circuitry for providing an amplitude compressed signal responsive to the applied sensed signal. The compression circuitry has a stepwise substantially linear transfer function responsive to a variable magnitude of the applied sensed signal. Signal processing circuitry is coupled to the compression circuitry for sequentially generating a digital signal representative of the sensed analog signal. Digital processing circuitry sequentially identifies a maximum peak signal for a predetermined time interval and provides linearity correction for the identified maximum peak signals and generates a display of the corrected peak signals.

Abstract: A circuit for generating successive points on a sine wave using the Coordinate Rotational Digital Computer (CORDIC) algorithm. An angle memory and an amplitude memory store respective angle and amplitude values from which a CORDIC logic processor calculates a point on a sine wave. A frequency memory stores an increment value unique to the frequency of the sine wave to be formed, and an arithmetic logic unit adds the increment value to the stored angle value after the point on the sine wave is calculated. The CORDIC logic processor then calculates the next point on the sine wave from the incremented angle value. A digital-to-analog converter may be used to provide an analog output signal.For generating multi-tone signals, the angle, amplitude and frequency memories are configured to store a plurality of angle, amplitude and increment values, and an address memory is connected to each memory for simultaneously addressing them.