Abstract: In one embodiment, the disclosed subject matter is a method to produce a substantially uniform, silicon-carbide layer over both dielectric materials and metal materials. In one example, the method includes forming a silicon-nitride layer over the dielectric materials and the metal materials, and forming the silicon carbide layer over the silicon-nitride layer. Other methods are disclosed.

Abstract: A method for depositing a silicon nitride layer on a stack is provided. The method comprises providing an atomic layer deposition, comprising a plurality of cycles, wherein each cycle comprises dosing the stack with a silicon containing precursor by providing a silicon containing precursor gas, providing an N2 plasma conversion, and providing an H2 plasma conversion.

Abstract: Methods, systems, and apparatus for plating a metal onto a work piece with a plating solution having a low oxygen concentration are described. In one aspect, a method includes reducing an oxygen concentration of a plating solution. The plating solution includes about 100 parts per million or less of an accelerator. After reducing the oxygen concentration of the plating solution, a wafer substrate is contacted with the plating solution in a plating cell. The oxygen concentration of the plating solution in the plating cell is about 1 part per million or less. A metal is electroplated with the plating solution onto the wafer substrate in the plating cell. After electroplating the metal onto the wafer substrate, an oxidizing strength of the plating solution is increased.

Abstract: Methods, systems, and apparatus for plating a metal onto a work piece with a plating solution having a low oxygen concentration are described. In one aspect, a method includes reducing an oxygen concentration of a plating solution. The plating solution includes about 100 parts per million or less of an accelerator. After reducing the oxygen concentration of the plating solution, a wafer substrate is contacted with the plating solution in a plating cell. The oxygen concentration of the plating solution in the plating cell is about 1 part per million or less. A metal is electroplated with the plating solution onto the wafer substrate in the plating cell. After electroplating the metal onto the wafer substrate, an oxidizing strength of the plating solution is increased.

Abstract: The present invention provides a process for improving the hardness and/or modulus of elasticity of a dielectric layer and a method for manufacturing an integrated circuit. The process for improving the hardness and/or modulus of elasticity of a dielectric layer, among other steps, includes providing a dielectric layer having a hardness and a modulus of elasticity, and subjecting the dielectric layer to an energy beam, thereby causing the hardness or modulus of elasticity to increase in value.

Abstract: The present invention, in one embodiment, provides a method of fabricating a microelectronics device 200. This embodiment comprises forming a liner 310 over a substrate 210 and a gate structure 230, subjecting the liner 310 to an electron beam 405 and depositing a pre-metal dielectric layer 415 over the liner 310.

Abstract: The present invention provides a process for improving the hardness and/or modulus of elasticity of a dielectric layer and a method for manufacturing an integrated circuit. The process for improving the hardness and/or modulus of elasticity of a dielectric layer, among other steps, includes providing a dielectric layer having a hardness and a modulus of elasticity, and subjecting the dielectric layer to an energy beam, thereby causing the hardness or modulus of elasticity to increase in value.

Abstract: The present invention provides an insulating layer 100 for an integrated circuit 110 comprising a porous silicon-based dielectric layer 120 located over a substrate 130. The insulating layer comprises a densified layer 140 comprising an uppermost portion 142 of the porous silicon-based dielectric layer.

Abstract: A process for forming nickel silicide and silicon nitride structure in a semiconductor integrated circuit device is described. Good adhesion between the nickel silicide and the silicon nitride is accomplished by passivating the nickel silicide surface with nitrogen. The passivation may be performed by treating the nickel silicide surface with plasma activated nitrogen species. An alternative passivation method is to cover the nickel silicide with a film of metal nitride and heat the substrate to about 500° C. Another alternative method is to sputter deposit silicon nitride on top of nickel silicide.

Abstract: A dual damascene process flow for forming interconnect lines and vias in which at least part of the via (116) is etched prior to the trench etch. A low-k material such as a thermoset organic polymer is used for the ILD (106) and IMD (110). After the at least partial via etch, a BARC (120) is deposited over the structure including in the via (116). Then, the trench (126) is patterned and etched. Although at least some of the BARC (120) material is removed during the trench etch, the bottom of the via (116) is protected.