Abstract: An apparatus for storing gloves includes a storage arm that has a first surface and a second surface that extends substantially parallel to the first surface. At least one notch is formed in the storage arm and extends from the first surface towards the second surface for defining a plurality of projections. At least one of the notch and the projection being capable of receiving a mouth of a glove.

Abstract: A single-wire serial communications bus has a master device and one or more slave devices. The slave devices are addressed according to a predetermined addressing scheme in an address space. The master device starts a transmission with a number of line state changes which define a clock period to be used by the slave devices in clocking and framing the serial data. This permits omitting a clock line, thus saving a pin and saving printed circuit board space. This also permits the slave devices to shut down their own clocks during periods of inactivity on the bus, thus saving power. Likewise the master device is able to shut down its clock during periods of bus inactivity.

Abstract: A system is provided for use with an on-chip fuse. If the fuse (40) is to be blown, the system blows the fuse, then performs a test read by comparing it with a larger-than-normal reference resistance (41, 42). If, even using the larger-than-normal reference resistance, the fuse reads as blown, then it is possible to be much more confident that the fuse will read correctly when compared against the normal reference resistance (42), even with aging and with variations of temperature and supply. For future reads during normal operation, the system compares it with the normal reference resistance (42). If, on the other hand, the fuse does not read as blown during the test read then the device can be rejected as a failed device.

Abstract: A system is provided for use with an on-chip fuse. If the fuse (40) is to be blown, the system blows the fuse, then performs a test read by comparing it with a larger-than-normal reference resistance (41, 42). If, even using the larger-than-normal reference resistance, the fuse reads as blown, then it is possible to be much more confident that the fuse will read correctly when compared against the normal reference resistance (42), even with aging and with variations of temperature and supply. For future reads during normal operation, the system compares it with the normal reference resistance (42). If, on the other hand, the fuse does not read as blown during the test read then the device can be rejected as a failed device.

Abstract: An improved oscillator system has a control logic block which has an input from an external device to which clock is being provided. The input controls a counter which counts cycles from the oscillator. If some predetermined number of cycles has passed in the absence of a predetermined input condition, then the oscillator halts, thus reducing power consumption by the oscillator system. Later, upon the predetermined input condition, the oscillator resumes oscillation. The system has improved noise immunity and permits a continuous-oscillation mode without the need of an extra pin or memory bit. The control logic block may also employ a counter which counts the number of times the predetermined input condition has occurred, and only after some predetermined number of occurrences does the oscillator-halting activity take place.

Abstract: A single-wire serial communications bus has a master device and one or more slave devices. The slave devices are addressed according to a predetermined addressing scheme in an address space. The master device starts a transmission with a number of line state changes which define a clock period to be used by the slave devices in clocking and framing the serial data. This permits omitting a clock line, thus saving a pin and saving printed circuit board space. This also permits the slave devices to shut down their own clocks during periods of inactivity on the bus, thus saving power. Likewise the master device is able to shut down its clock during periods of bus inactivity.

Abstract: A slave clock generation system and method suitable for use with synchronous telecommunications networks generates one or more slave clocks from a selected reference clock using a direct digital synthesis technique. A multiplexer selects a reference clock from a number of available sources, each of which can be at its own spot frequency, based on a predetermined selection order. Toggle detectors monitor each of the available clock sources, and block the selection of any that are not within a specified frequency range. A local oscillator establishes short-term and long-term measurement periods; the cycles of the selected reference clock are counted over consecutive short-term measurement periods to determine the relative frequency of the selected clock with respect to the frequency of the local oscillator. The cycle counts are fed to a phase-to-clock converter, which produces a slave clock output having a frequency that varies with the relative frequency measured for the selected clock.