Abstract: Disclosed herein are methods for forming vertical field-effect-transistor (vFET). In some embodiments, a method includes providing a device structure including a plurality of pillars extending from a base layer, forming a capping layer over the device structure, and forming a drain in an upper section of each of the plurality of pillars by performing an angled implant to each of the plurality of pillars. The angled implant may be delivered at a non-zero angle of inclination relative to a perpendicular extending from a top surface of the base layer. The method may further include etching the device structure to remove the capping layer from along a lower section of each of the plurality of pillars, wherein the capping layer remains along the upper section of each of the plurality of pillars.

Abstract: In one embodiment, a method may include providing a substrate, comprising a plurality of surface features, an isolation layer, disposed between the plurality of surface features, and a substrate base, disposed subjacent the isolation layer and the plurality of surface features, wherein the plurality of surface features extend above a surface of the isolation layer. The method may include directing a low energy ion beam to the substrate, when the substrate is heated at a targeted temperature, wherein an altered layer is formed within an outer portion of the isolation layer, and wherein an inner portion of the isolation layer is not implanted.

Abstract: Disclosed herein are methods for forming vertical field-effect-transistor (vFET). In some embodiments, a method includes providing a device structure including a plurality of pillars extending from a base layer, forming a capping layer over the device structure, and forming a drain in an upper section of each of the plurality of pillars by performing an angled implant to each of the plurality of pillars. The angled implant may be delivered at a non-zero angle of inclination relative to a perpendicular extending from a top surface of the base layer. The method may further include etching the device structure to remove the capping layer from along a lower section of each of the plurality of pillars, wherein the capping layer remains along the upper section of each of the plurality of pillars.

Abstract: In one embodiment, a method may include providing a substrate, comprising a plurality of surface features, an isolation layer, disposed between the plurality of surface features, and a substrate base, disposed subjacent the isolation layer and the plurality of surface features, wherein the plurality of surface features extend above a surface of the isolation layer. The method may include directing a low energy ion beam to the substrate, when the substrate is heated at a targeted temperature, wherein an altered layer is formed within an outer portion of the isolation layer, and wherein an inner portion of the isolation layer is not implanted.

Abstract: A method may include performing a chemical mechanical polishing (CMP) etch of a fin assembly disposed on a substrate, the fin assembly comprising a plurality of fin structures coated with an oxide layer, wherein as a result of the CMP etch, a first portion of the oxide layer is removed, and the fin structures remain covered with oxide. The method may further include performing a selective area processing (SAP) etch using ions, wherein a second portion of the oxide layer is removed in a non-uniform manner, wherein after the SAP etch, the fin structures remain covered with oxide.

Abstract: A method may include performing a chemical mechanical polishing (CMP) etch of a fin assembly disposed on a substrate, the fin assembly comprising a plurality of fin structures coated with an oxide layer, wherein as a result of the CMP etch, a first portion of the oxide layer is removed, and the fin structures remain covered with oxide. The method may further include performing a selective area processing (SAP) etch using ions, wherein a second portion of the oxide layer is removed in a non-uniform manner, wherein after the SAP etch, the fin structures remain covered with oxide.

Abstract: A method is provided for fabricating a strained MOS device having a silicon germanium on insulator (SGOI) substrate that includes a layer of monocrystalline silicon germanium material characterized by a first lattice constant. A strained silicon layer is formed over the layer of monocrystalline silicon germanium material. A layer of gate electrode material is patterned to form a gate electrode overlying a channel region. The strained silicon layer is disposed between the gate electrode and the channel region. First recess and second recesses are etched into the layer of monocrystalline silicon germanium material. A layer of monocrystalline semiconductor material is then epitaxially grown to fill the first and second recesses such that it is embedded at the opposing sides of the channel region. The layer of monocrystalline semiconductor material comprises silicon and germanium, and is characterized by a second lattice constant less than the first lattice constant.

Abstract: An MOS device having enhanced mobility and a method for its fabrication are provided. The method comprises providing a P-type monocrystalline silicon germanium substrate having a first lattice constant and a channel region at the substrate surface, forming a gate insulator layer on the substrate, forming a gate electrode having a first sidewall and a second sidewall overlying the channel. First and second recesses are etched into the substrate in alignment with the first and the second gate electrode sidewalls, respectively. The recesses are filled by epitaxially growing a layer of embedded monocrystalline semiconductor material characterized by a second lattice constant less than the first lattice constant to impart a tensile strain on the channel region.

Abstract: A semiconductor device comprising a substrate having a first crystal orientation is provided. A first insulating layer overlies the substrate and a plurality of silicon layers overlie the first insulating layer. A first silicon layer comprises silicon having a second crystal orientation and a crystal plane. A second silicon layer comprises silicon having the second crystal orientation and a crystal plane that is substantially orthogonal to the crystal plane of the first silicon layer. Because holes have higher mobility in the (110) plane than the (100) plane, while electrons have higher mobility in (100) plane than the (110) plane, semiconductor device performance can be enhanced by the selection of silicon layers with certain crystal plane orientations. In addition, a method of forming a semiconductor device is provided.