Abstract: A mechanism for managing packetized data transfers in a system including a transmitting and a receiving device. The transmitting device may transmit data to the receiving device in a plurality of packets, each packet a predetermined number of data bytes wide. The transmitting device may include a transfer count unit to maintain a data transfer count based on a number of transmitted data bytes. The receiving device may program the transmitting device with a transfer count mark, which may be a number that corresponds to a specific count of the data transfer count. The transmitting device may calculate a difference between the data transfer count and the transfer count mark. If the difference between the transfer count and the transfer count mark is less than the predetermined number, the transmitting device may transmit a short data packet having less than the predetermined number of data bytes to the receiving device.

Abstract: A system and method for buffering bidirectional digital I/O lines. The system (e.g., data acquisition system) may comprise a device including circuitry for buffering bidirectional digital lines. A first IC of the device preferably includes a first and a second bidirectional buffer coupled to a first bidirectional digital I/O line, and a second IC of the device preferably includes a third bidirectional buffer. The first IC and the second IC may also each include a control unit to control a driving direction of the corresponding bidirectional buffers independently to change the direction of a data flow through the first bidirectional digital I/O line from a first direction to a second direction. The driving direction of the bidirectional buffers may be changed at different times in a particular sequence, and the order may depend on whether the direction change is from the output direction to the input direction or vice versa.

Abstract: A digitizer for use in a measurement system. The digitizer acquires data from an external source, and includes a static random access memory (SRAM) which stores a scan list comprising entries specifying digitizer operations such as switch time, settle time, measure time, looping, and mathematical operation specifications such as scaling, adding, and averaging specifications. The looping specification may include instructions to repeatedly execute one or more entries in the scan list. The digitizer includes a programmable logic element (e.g. an FPGA) coupled to the SRAM which accesses and executes the scan list to acquire analog signals from the source. The digitizer may include an analog-to-digital converter to convert the analog signals to digital signals, as well as a multiplexer to read the analog signals from multiple channels, a signal conditioner to modify the analog signals from the multiplexer, and an amplifier to amplify the analog signals from the signal conditioner.

Abstract: A digitizer for use in a measurement system. The digitizer acquires data from an external source, and includes a static random access memory (SRAM) which stores a scan list comprising entries specifying digitizer operations such as switch time, settle time, measure time, looping, and mathematical operation specifications such as scaling, adding, and averaging specifications. The looping specification may include instructions to repeatedly execute one or more entries in the scan list. The digitizer includes a programmable logic element (e.g. an FPGA) coupled to the SRAM which accesses and executes the scan list to acquire analog signals from the source. The digitizer may include an analog-to-digital converter to convert the analog signals to digital signals, as well as a multiplexer to read the analog signals from multiple channels, a signal conditioner to modify the analog signals from the multiplexer, and an amplifier to amplify the analog signals from the signal conditioner.