Patents by Inventor Andrew Morten
Andrew Morten has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12109192Abstract: The invention relates to a pharmaceutically acceptable acid addition salt of: (i) S-pindolol; and (ii) an organic acid, wherein the organic acid has: a pKal of greater than or equal to 2.5; and a chemical formula of CxHy(CO2H)z, where x is from 1 to 10, y is from 2 to 20 and z is 1 or 2. The pharmaceutically acceptable acid addition salt is useful in treating conditions such as cachexia, sarcopenia, a neuromuscular disorder and muscle weakness.Type: GrantFiled: March 31, 2021Date of Patent: October 8, 2024Assignee: ACTIMED THERAPEUTICS LTDInventors: Robin Chandra Bhattacherjee, Andrew Justin Stewart Coats, Elaine Morten, Ronnie Maxwell Lawrence, Jaclyn Raeburn, Kiara Marissa Lobato, Jonathan James Loughrey
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Publication number: 20240311194Abstract: A system and method for a computing tile of a multi-tiled integrated circuit includes a plurality of distinct tile computing circuits, wherein each of the plurality of distinct tile computing circuits is configured to receive fixed-length instructions; a token-informed task scheduler that: tracks one or more of a plurality of distinct tokens emitted by one or more of the plurality of distinct tile computing circuits; and selects a distinct computation task of a plurality of distinct computation tasks based on the tracking; and a work queue buffer that: contains a plurality of distinct fixed-length instructions, wherein each one of the fixed-length instructions is associated with one of the plurality of distinct computation tasks; and transmits one of the plurality of distinct fixed-length instructions to one or more of the plurality of distinct tile computing circuits based on the selection of the distinct computation task by the token-informed task scheduler.Type: ApplicationFiled: May 23, 2024Publication date: September 19, 2024Applicant: Mythic, Inc.Inventors: Malav Parikh, Sergio Schuler, Vimal Reddy, Zainab Zaidi, Paul Toth, Adam Caughron, Bryant Sorensen, Alex Dang-Tran, Scott Johnson, Raul Garibay, Andrew Morten, David Fick
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Patent number: 12014214Abstract: A system and method for a computing tile of a multi-tiled integrated circuit includes a plurality of distinct tile computing circuits, wherein each of the plurality of distinct tile computing circuits is configured to receive fixed-length instructions; a token-informed task scheduler that: tracks one or more of a plurality of distinct tokens emitted by one or more of the plurality of distinct tile computing circuits; and selects a distinct computation task of a plurality of distinct computation tasks based on the tracking; and a work queue buffer that: contains a plurality of distinct fixed-length instructions, wherein each one of the fixed-length instructions is associated with one of the plurality of distinct computation tasks; and transmits one of the plurality of distinct fixed-length instructions to one or more of the plurality of distinct tile computing circuits based on the selection of the distinct computation task by the token-informed task scheduler.Type: GrantFiled: April 15, 2021Date of Patent: June 18, 2024Assignee: Mythic, Inc.Inventors: Malav Parikh, Sergio Schuler, Vimal Reddy, Zainab Zaidi, Paul Toth, Adam Caughron, Bryant Sorensen, Alex Dang-Tran, Scott Johnson, Raul Garibay, Andrew Morten, David Fick
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Publication number: 20240037314Abstract: Systems and methods for optimizing data flow in an integrated circuit includes creating a task graph based on transforming an optimized network graph for a neural network application, wherein creating the task graph includes: enumerating a plurality of distinct tasks based on a decomposition of each of a plurality of network operations of the optimized network graph; and allocating a data buffer to each of pairs of dependent tasks of the plurality of distinct tasks based on the decomposition of each of the plurality of network operations of the optimized network graph; encoding a token-informed task scheduler based on a composition of the task graph, wherein the encoding the token-informed task scheduler includes: programming the token-informed task scheduler to cause an execution of the plurality of distinct tasks based on identifying a state of a respective data buffer between each of the pairs of dependent tasks.Type: ApplicationFiled: October 10, 2023Publication date: February 1, 2024Inventors: Pei-Ci Wu, Andrew Morten, Anthony Romano, Balaji Iyer, Alexander Dang-Tran, Eric Stotzer, David Fick
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Patent number: 11822376Abstract: Systems and methods for optimizing data flow in an integrated circuit includes creating a task graph based on transforming an optimized network graph for a neural network application, wherein creating the task graph includes: enumerating a plurality of distinct tasks based on a decomposition of each of a plurality of network operations of the optimized network graph; and allocating a data buffer to each of pairs of dependent tasks of the plurality of distinct tasks based on the decomposition of each of the plurality of network operations of the optimized network graph; encoding a token-informed task scheduler based on a composition of the task graph, wherein the encoding the token-informed task scheduler includes: programming the token-informed task scheduler to cause an execution of the plurality of distinct tasks based on identifying a state of a respective data buffer between each of the pairs of dependent tasks.Type: GrantFiled: June 4, 2021Date of Patent: November 21, 2023Assignee: Mythic, Inc.Inventors: Pei-Ci Wu, Andrew Morten, Anthony Romano, Balaji Iyer, Alexander Dang-Tran, Eric Stotzer, David Fick
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Publication number: 20230222174Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.Type: ApplicationFiled: March 16, 2023Publication date: July 13, 2023Inventors: David Fick, Michael Henry, Laura Fick, Malav Parikh, Skylar Akrzyniarz, Scott Johnson, Pei-Ci Wu, Andrew Morten
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Patent number: 11625519Abstract: A system and method for minimizing a total physical size of data buffers for executing an artificial neural network (ANN) on an integrated circuit includes implementing a buffer-sizing simulation based on sourcing a task graph of the ANN, wherein: (i) the task graph includes a plurality of distinct data buffers, wherein each of the plurality of distinct data buffers is assigned to at least one write operation and at least one read operation; (ii) the buffer-sizing simulation, when executed, computes an estimated physical size for each of a plurality of distinct data buffers for implementing the artificial neural network on a mixed-signal integrated circuit; and (iii) configuring the buffer-sizing simulation includes setting simulation parameters that include buffer-size minimization parameters and buffer data throughput optimization parameters; and generating an estimate of a physical size for each of the plurality of distinct data buffers based on the implementation of the buffer-sizing simulation.Type: GrantFiled: April 4, 2022Date of Patent: April 11, 2023Assignee: Mythic, Inc.Inventors: Andrew Morten, Eric Stotzer, Michael Siegrist, David Fick
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Patent number: 11615165Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.Type: GrantFiled: March 5, 2021Date of Patent: March 28, 2023Assignee: Mythic, Inc.Inventors: David Fick, Michael Henry, Laura Fick, Malav Parikh, Skylar Skrzyniarz, Scott Johnson, Pei-Ci Wu, Andrew Morten
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Publication number: 20220318467Abstract: A system and method for minimizing a total physical size of data buffers for executing an artificial neural network (ANN) on an integrated circuit includes implementing a buffer-sizing simulation based on sourcing a task graph of the ANN, wherein: (i) the task graph includes a plurality of distinct data buffers, wherein each of the plurality of distinct data buffers is assigned to at least one write operation and at least one read operation; (ii) the buffer-sizing simulation, when executed, computes an estimated physical size for each of a plurality of distinct data buffers for implementing the artificial neural network on a mixed-signal integrated circuit; and (iii) configuring the buffer-sizing simulation includes setting simulation parameters that include buffer-size minimization parameters and buffer data throughput optimization parameters; and generating an estimate of a physical size for each of the plurality of distinct data buffers based on the implementation of the buffer-sizing simulation.Type: ApplicationFiled: April 4, 2022Publication date: October 6, 2022Inventors: Andrew Morten, Eric Stotzer, Michael Siegrist, David Fick
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Publication number: 20210294960Abstract: Systems and methods for optimizing data flow in an integrated circuit includes creating a task graph based on transforming an optimized network graph for a neural network application, wherein creating the task graph includes: enumerating a plurality of distinct tasks based on a decomposition of each of a plurality of network operations of the optimized network graph; and allocating a data buffer to each of pairs of dependent tasks of the plurality of distinct tasks based on the decomposition of each of the plurality of network operations of the optimized network graph; encoding a token-informed task scheduler based on a composition of the task graph, wherein the encoding the token-informed task scheduler includes: programming the token-informed task scheduler to cause an execution of the plurality of distinct tasks based on identifying a state of a respective data buffer between each of the pairs of dependent tasks.Type: ApplicationFiled: June 4, 2021Publication date: September 23, 2021Inventors: Pei-Ci Wu, Andrew Morten, Anthony Romano, Balaji Iyer, Alexander Dang-Tran, Eric Stotzer, David Fick
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Publication number: 20210287077Abstract: Systems and methods for improving a computational performance of a mixed-signal integrated circuit includes identifying a suboptimal graph component of a computation graph of a subject application, wherein: (i) the computation graph comprises a plurality of graphical nodes representing computational operations and a plurality of graphical edges representing data dependencies between the graphical nodes, and (ii) the suboptimal graph component comprises a subset of the plurality of graphical nodes and the plurality of graphical edges that do not satisfy an optimal operation threshold; at compile time, selectively applying an optimizing transformation to the suboptimal graph component based on attributes of a first activation function within the suboptimal graph component, wherein the optimization transformation, when applied, transforms the suboptimal graph component to an optimal graph component that satisfies the optimal operation threshold; and reconstructing the computation graph using the optimal graph coType: ApplicationFiled: January 15, 2021Publication date: September 16, 2021Inventors: Andrew Morten, Eric Stotzer, Pei-Ci Wu, Michail Tzoufras, David Fick
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Publication number: 20210232435Abstract: A system and method for a computing tile of a multi-tiled integrated circuit includes a plurality of distinct tile computing circuits, wherein each of the plurality of distinct tile computing circuits is configured to receive fixed-length instructions; a token-informed task scheduler that: tracks one or more of a plurality of distinct tokens emitted by one or more of the plurality of distinct tile computing circuits; and selects a distinct computation task of a plurality of distinct computation tasks based on the tracking; and a work queue buffer that: contains a plurality of distinct fixed-length instructions, wherein each one of the fixed-length instructions is associated with one of the plurality of distinct computation tasks; and transmits one of the plurality of distinct fixed-length instructions to one or more of the plurality of distinct tile computing circuits based on the selection of the distinct computation task by the token-informed task scheduler.Type: ApplicationFiled: April 15, 2021Publication date: July 29, 2021Inventors: Malav Parikh, Sergio Schuler, Vimal Reddy, Zainab Zaidi, Paul Toth, Adam Caughron, Bryant Sorensen, Alex Dang-Tran, Scott Johnson, Raul Garibay, Andrew Morten, David Fick
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Patent number: 11068641Abstract: Systems and methods for optimizing data flow in an integrated circuit includes creating a task graph based on transforming an optimized network graph for a neural network application, wherein creating the task graph includes: enumerating a plurality of distinct tasks based on a decomposition of each of a plurality of network operations of the optimized network graph; and allocating a data buffer to each of pairs of dependent tasks of the plurality of distinct tasks based on the decomposition of each of the plurality of network operations of the optimized network graph; encoding a token-informed task scheduler based on a composition of the task graph, wherein the encoding the token-informed task scheduler includes: programming the token-informed task scheduler to cause an execution of the plurality of distinct tasks based on identifying a state of a respective data buffer between each of the pairs of dependent tasks.Type: GrantFiled: March 4, 2021Date of Patent: July 20, 2021Assignee: Mythic, Inc.Inventors: Pei-Ci Wu, Andrew Morten, Anthony Romano, Balaji Iyer, Alexander Dang-Tran, Eric Stotzer, David Fick
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Publication number: 20210192010Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.Type: ApplicationFiled: March 5, 2021Publication date: June 24, 2021Inventors: David Fick, Michael Henry, Laura Fick, Malav Parikh, Skylar Akrzyniarz, Scott Johnson, Pei-Ci Wu, Andrew Morten
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Publication number: 20210157648Abstract: A system and method for a computing tile of a multi-tiled integrated circuit includes a plurality of distinct tile computing circuits, wherein each of the plurality of distinct tile computing circuits is configured to receive fixed-length instructions; a token-informed task scheduler that: tracks one or more of a plurality of distinct tokens emitted by one or more of the plurality of distinct tile computing circuits; and selects a distinct computation task of a plurality of distinct computation tasks based on the tracking; and a work queue buffer that: contains a plurality of distinct fixed-length instructions, wherein each one of the fixed-length instructions is associated with one of the plurality of distinct computation tasks; and transmits one of the plurality of distinct fixed-length instructions to one or more of the plurality of distinct tile computing circuits based on the selection of the distinct computation task by the token-informed task scheduler.Type: ApplicationFiled: November 24, 2020Publication date: May 27, 2021Inventors: Malav Parikh, Sergio Schuler, Vimal Reddy, Zainab Zaidi, Paul Toth, Adam Caughron, Bryant Sorensen, Alexander Dang-Tran, Scott Johnson, Raul Garibay, Andrew Morten, David Fick
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Patent number: 11016810Abstract: A system and method for a computing tile of a multi-tiled integrated circuit includes a plurality of distinct tile computing circuits, wherein each of the plurality of distinct tile computing circuits is configured to receive fixed-length instructions; a token-informed task scheduler that: tracks one or more of a plurality of distinct tokens emitted by one or more of the plurality of distinct tile computing circuits; and selects a distinct computation task of a plurality of distinct computation tasks based on the tracking; and a work queue buffer that: contains a plurality of distinct fixed-length instructions, wherein each one of the fixed-length instructions is associated with one of the plurality of distinct computation tasks; and transmits one of the plurality of distinct fixed-length instructions to one or more of the plurality of distinct tile computing circuits based on the selection of the distinct computation task by the token-informed task scheduler.Type: GrantFiled: November 24, 2020Date of Patent: May 25, 2021Assignee: Mythic, Inc.Inventors: Malav Parikh, Sergio Schuler, Vimal Reddy, Zainab Zaidi, Paul Toth, Adam Caughron, Bryant Sorensen, Alex Dang-Tran, Scott Johnson, Raul Garibay, Andrew Morten, David Fick
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Patent number: 10977339Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.Type: GrantFiled: November 14, 2019Date of Patent: April 13, 2021Assignee: Mythic, Inc.Inventors: David Fick, Michael Henry, Laura Fick, Malav Parikh, Skylar Skrzyniarz, Scott Johnson, Pei-Ci Wu, Andrew Morten
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Patent number: 10929748Abstract: Systems and methods for improving a computational performance of a mixed-signal integrated circuit includes identifying a suboptimal graph component of a computation graph of a subject application, wherein: (i) the computation graph comprises a plurality of graphical nodes representing computational operations and a plurality of graphical edges representing data dependencies between the graphical nodes, and (ii) the suboptimal graph component comprises a subset of the plurality of graphical nodes and the plurality of graphical edges that do not satisfy an optimal operation threshold; at compile time, selectively applying an optimizing transformation to the suboptimal graph component based on attributes of a first activation function within the suboptimal graph component, wherein the optimization transformation, when applied, transforms the suboptimal graph component to an optimal graph component that satisfies the optimal operation threshold; and reconstructing the computation graph using the optimal graph coType: GrantFiled: October 1, 2020Date of Patent: February 23, 2021Assignee: Mythic, Inc.Inventors: Andrew Morten, Eric Stotzer, Pei-Ci Wu, Michail Tzoufras, David Fick
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Publication number: 20200081937Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.Type: ApplicationFiled: November 14, 2019Publication date: March 12, 2020Inventors: David Fick, Michael Henry, Laura Fick, Malav Parikh, Skylar Skrzyniarz, Scott Johnson, Pei-Ci Wu, Andrew Morten
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Patent number: 10515136Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.Type: GrantFiled: May 2, 2019Date of Patent: December 24, 2019Assignee: Mythic, Inc.Inventors: David Fick, Michael Henry, Laura Fick, Malav Parikh, Skylar Skrzyniarz, Scott Johnson, Pei-Ci Wu, Andrew Morten