Patents by Inventor Andrew Morten

Andrew Morten has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12109192
    Abstract: The invention relates to a pharmaceutically acceptable acid addition salt of: (i) S-pindolol; and (ii) an organic acid, wherein the organic acid has: a pKal of greater than or equal to 2.5; and a chemical formula of CxHy(CO2H)z, where x is from 1 to 10, y is from 2 to 20 and z is 1 or 2. The pharmaceutically acceptable acid addition salt is useful in treating conditions such as cachexia, sarcopenia, a neuromuscular disorder and muscle weakness.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: October 8, 2024
    Assignee: ACTIMED THERAPEUTICS LTD
    Inventors: Robin Chandra Bhattacherjee, Andrew Justin Stewart Coats, Elaine Morten, Ronnie Maxwell Lawrence, Jaclyn Raeburn, Kiara Marissa Lobato, Jonathan James Loughrey
  • Publication number: 20240311194
    Abstract: A system and method for a computing tile of a multi-tiled integrated circuit includes a plurality of distinct tile computing circuits, wherein each of the plurality of distinct tile computing circuits is configured to receive fixed-length instructions; a token-informed task scheduler that: tracks one or more of a plurality of distinct tokens emitted by one or more of the plurality of distinct tile computing circuits; and selects a distinct computation task of a plurality of distinct computation tasks based on the tracking; and a work queue buffer that: contains a plurality of distinct fixed-length instructions, wherein each one of the fixed-length instructions is associated with one of the plurality of distinct computation tasks; and transmits one of the plurality of distinct fixed-length instructions to one or more of the plurality of distinct tile computing circuits based on the selection of the distinct computation task by the token-informed task scheduler.
    Type: Application
    Filed: May 23, 2024
    Publication date: September 19, 2024
    Applicant: Mythic, Inc.
    Inventors: Malav Parikh, Sergio Schuler, Vimal Reddy, Zainab Zaidi, Paul Toth, Adam Caughron, Bryant Sorensen, Alex Dang-Tran, Scott Johnson, Raul Garibay, Andrew Morten, David Fick
  • Patent number: 12014214
    Abstract: A system and method for a computing tile of a multi-tiled integrated circuit includes a plurality of distinct tile computing circuits, wherein each of the plurality of distinct tile computing circuits is configured to receive fixed-length instructions; a token-informed task scheduler that: tracks one or more of a plurality of distinct tokens emitted by one or more of the plurality of distinct tile computing circuits; and selects a distinct computation task of a plurality of distinct computation tasks based on the tracking; and a work queue buffer that: contains a plurality of distinct fixed-length instructions, wherein each one of the fixed-length instructions is associated with one of the plurality of distinct computation tasks; and transmits one of the plurality of distinct fixed-length instructions to one or more of the plurality of distinct tile computing circuits based on the selection of the distinct computation task by the token-informed task scheduler.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: June 18, 2024
    Assignee: Mythic, Inc.
    Inventors: Malav Parikh, Sergio Schuler, Vimal Reddy, Zainab Zaidi, Paul Toth, Adam Caughron, Bryant Sorensen, Alex Dang-Tran, Scott Johnson, Raul Garibay, Andrew Morten, David Fick
  • Publication number: 20240037314
    Abstract: Systems and methods for optimizing data flow in an integrated circuit includes creating a task graph based on transforming an optimized network graph for a neural network application, wherein creating the task graph includes: enumerating a plurality of distinct tasks based on a decomposition of each of a plurality of network operations of the optimized network graph; and allocating a data buffer to each of pairs of dependent tasks of the plurality of distinct tasks based on the decomposition of each of the plurality of network operations of the optimized network graph; encoding a token-informed task scheduler based on a composition of the task graph, wherein the encoding the token-informed task scheduler includes: programming the token-informed task scheduler to cause an execution of the plurality of distinct tasks based on identifying a state of a respective data buffer between each of the pairs of dependent tasks.
    Type: Application
    Filed: October 10, 2023
    Publication date: February 1, 2024
    Inventors: Pei-Ci Wu, Andrew Morten, Anthony Romano, Balaji Iyer, Alexander Dang-Tran, Eric Stotzer, David Fick
  • Patent number: 11822376
    Abstract: Systems and methods for optimizing data flow in an integrated circuit includes creating a task graph based on transforming an optimized network graph for a neural network application, wherein creating the task graph includes: enumerating a plurality of distinct tasks based on a decomposition of each of a plurality of network operations of the optimized network graph; and allocating a data buffer to each of pairs of dependent tasks of the plurality of distinct tasks based on the decomposition of each of the plurality of network operations of the optimized network graph; encoding a token-informed task scheduler based on a composition of the task graph, wherein the encoding the token-informed task scheduler includes: programming the token-informed task scheduler to cause an execution of the plurality of distinct tasks based on identifying a state of a respective data buffer between each of the pairs of dependent tasks.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: November 21, 2023
    Assignee: Mythic, Inc.
    Inventors: Pei-Ci Wu, Andrew Morten, Anthony Romano, Balaji Iyer, Alexander Dang-Tran, Eric Stotzer, David Fick
  • Publication number: 20230222174
    Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.
    Type: Application
    Filed: March 16, 2023
    Publication date: July 13, 2023
    Inventors: David Fick, Michael Henry, Laura Fick, Malav Parikh, Skylar Akrzyniarz, Scott Johnson, Pei-Ci Wu, Andrew Morten
  • Patent number: 11625519
    Abstract: A system and method for minimizing a total physical size of data buffers for executing an artificial neural network (ANN) on an integrated circuit includes implementing a buffer-sizing simulation based on sourcing a task graph of the ANN, wherein: (i) the task graph includes a plurality of distinct data buffers, wherein each of the plurality of distinct data buffers is assigned to at least one write operation and at least one read operation; (ii) the buffer-sizing simulation, when executed, computes an estimated physical size for each of a plurality of distinct data buffers for implementing the artificial neural network on a mixed-signal integrated circuit; and (iii) configuring the buffer-sizing simulation includes setting simulation parameters that include buffer-size minimization parameters and buffer data throughput optimization parameters; and generating an estimate of a physical size for each of the plurality of distinct data buffers based on the implementation of the buffer-sizing simulation.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: April 11, 2023
    Assignee: Mythic, Inc.
    Inventors: Andrew Morten, Eric Stotzer, Michael Siegrist, David Fick
  • Patent number: 11615165
    Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: March 28, 2023
    Assignee: Mythic, Inc.
    Inventors: David Fick, Michael Henry, Laura Fick, Malav Parikh, Skylar Skrzyniarz, Scott Johnson, Pei-Ci Wu, Andrew Morten
  • Publication number: 20220318467
    Abstract: A system and method for minimizing a total physical size of data buffers for executing an artificial neural network (ANN) on an integrated circuit includes implementing a buffer-sizing simulation based on sourcing a task graph of the ANN, wherein: (i) the task graph includes a plurality of distinct data buffers, wherein each of the plurality of distinct data buffers is assigned to at least one write operation and at least one read operation; (ii) the buffer-sizing simulation, when executed, computes an estimated physical size for each of a plurality of distinct data buffers for implementing the artificial neural network on a mixed-signal integrated circuit; and (iii) configuring the buffer-sizing simulation includes setting simulation parameters that include buffer-size minimization parameters and buffer data throughput optimization parameters; and generating an estimate of a physical size for each of the plurality of distinct data buffers based on the implementation of the buffer-sizing simulation.
    Type: Application
    Filed: April 4, 2022
    Publication date: October 6, 2022
    Inventors: Andrew Morten, Eric Stotzer, Michael Siegrist, David Fick
  • Publication number: 20210294960
    Abstract: Systems and methods for optimizing data flow in an integrated circuit includes creating a task graph based on transforming an optimized network graph for a neural network application, wherein creating the task graph includes: enumerating a plurality of distinct tasks based on a decomposition of each of a plurality of network operations of the optimized network graph; and allocating a data buffer to each of pairs of dependent tasks of the plurality of distinct tasks based on the decomposition of each of the plurality of network operations of the optimized network graph; encoding a token-informed task scheduler based on a composition of the task graph, wherein the encoding the token-informed task scheduler includes: programming the token-informed task scheduler to cause an execution of the plurality of distinct tasks based on identifying a state of a respective data buffer between each of the pairs of dependent tasks.
    Type: Application
    Filed: June 4, 2021
    Publication date: September 23, 2021
    Inventors: Pei-Ci Wu, Andrew Morten, Anthony Romano, Balaji Iyer, Alexander Dang-Tran, Eric Stotzer, David Fick
  • Publication number: 20210287077
    Abstract: Systems and methods for improving a computational performance of a mixed-signal integrated circuit includes identifying a suboptimal graph component of a computation graph of a subject application, wherein: (i) the computation graph comprises a plurality of graphical nodes representing computational operations and a plurality of graphical edges representing data dependencies between the graphical nodes, and (ii) the suboptimal graph component comprises a subset of the plurality of graphical nodes and the plurality of graphical edges that do not satisfy an optimal operation threshold; at compile time, selectively applying an optimizing transformation to the suboptimal graph component based on attributes of a first activation function within the suboptimal graph component, wherein the optimization transformation, when applied, transforms the suboptimal graph component to an optimal graph component that satisfies the optimal operation threshold; and reconstructing the computation graph using the optimal graph co
    Type: Application
    Filed: January 15, 2021
    Publication date: September 16, 2021
    Inventors: Andrew Morten, Eric Stotzer, Pei-Ci Wu, Michail Tzoufras, David Fick
  • Publication number: 20210232435
    Abstract: A system and method for a computing tile of a multi-tiled integrated circuit includes a plurality of distinct tile computing circuits, wherein each of the plurality of distinct tile computing circuits is configured to receive fixed-length instructions; a token-informed task scheduler that: tracks one or more of a plurality of distinct tokens emitted by one or more of the plurality of distinct tile computing circuits; and selects a distinct computation task of a plurality of distinct computation tasks based on the tracking; and a work queue buffer that: contains a plurality of distinct fixed-length instructions, wherein each one of the fixed-length instructions is associated with one of the plurality of distinct computation tasks; and transmits one of the plurality of distinct fixed-length instructions to one or more of the plurality of distinct tile computing circuits based on the selection of the distinct computation task by the token-informed task scheduler.
    Type: Application
    Filed: April 15, 2021
    Publication date: July 29, 2021
    Inventors: Malav Parikh, Sergio Schuler, Vimal Reddy, Zainab Zaidi, Paul Toth, Adam Caughron, Bryant Sorensen, Alex Dang-Tran, Scott Johnson, Raul Garibay, Andrew Morten, David Fick
  • Patent number: 11068641
    Abstract: Systems and methods for optimizing data flow in an integrated circuit includes creating a task graph based on transforming an optimized network graph for a neural network application, wherein creating the task graph includes: enumerating a plurality of distinct tasks based on a decomposition of each of a plurality of network operations of the optimized network graph; and allocating a data buffer to each of pairs of dependent tasks of the plurality of distinct tasks based on the decomposition of each of the plurality of network operations of the optimized network graph; encoding a token-informed task scheduler based on a composition of the task graph, wherein the encoding the token-informed task scheduler includes: programming the token-informed task scheduler to cause an execution of the plurality of distinct tasks based on identifying a state of a respective data buffer between each of the pairs of dependent tasks.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: July 20, 2021
    Assignee: Mythic, Inc.
    Inventors: Pei-Ci Wu, Andrew Morten, Anthony Romano, Balaji Iyer, Alexander Dang-Tran, Eric Stotzer, David Fick
  • Publication number: 20210192010
    Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.
    Type: Application
    Filed: March 5, 2021
    Publication date: June 24, 2021
    Inventors: David Fick, Michael Henry, Laura Fick, Malav Parikh, Skylar Akrzyniarz, Scott Johnson, Pei-Ci Wu, Andrew Morten
  • Publication number: 20210157648
    Abstract: A system and method for a computing tile of a multi-tiled integrated circuit includes a plurality of distinct tile computing circuits, wherein each of the plurality of distinct tile computing circuits is configured to receive fixed-length instructions; a token-informed task scheduler that: tracks one or more of a plurality of distinct tokens emitted by one or more of the plurality of distinct tile computing circuits; and selects a distinct computation task of a plurality of distinct computation tasks based on the tracking; and a work queue buffer that: contains a plurality of distinct fixed-length instructions, wherein each one of the fixed-length instructions is associated with one of the plurality of distinct computation tasks; and transmits one of the plurality of distinct fixed-length instructions to one or more of the plurality of distinct tile computing circuits based on the selection of the distinct computation task by the token-informed task scheduler.
    Type: Application
    Filed: November 24, 2020
    Publication date: May 27, 2021
    Inventors: Malav Parikh, Sergio Schuler, Vimal Reddy, Zainab Zaidi, Paul Toth, Adam Caughron, Bryant Sorensen, Alexander Dang-Tran, Scott Johnson, Raul Garibay, Andrew Morten, David Fick
  • Patent number: 11016810
    Abstract: A system and method for a computing tile of a multi-tiled integrated circuit includes a plurality of distinct tile computing circuits, wherein each of the plurality of distinct tile computing circuits is configured to receive fixed-length instructions; a token-informed task scheduler that: tracks one or more of a plurality of distinct tokens emitted by one or more of the plurality of distinct tile computing circuits; and selects a distinct computation task of a plurality of distinct computation tasks based on the tracking; and a work queue buffer that: contains a plurality of distinct fixed-length instructions, wherein each one of the fixed-length instructions is associated with one of the plurality of distinct computation tasks; and transmits one of the plurality of distinct fixed-length instructions to one or more of the plurality of distinct tile computing circuits based on the selection of the distinct computation task by the token-informed task scheduler.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: May 25, 2021
    Assignee: Mythic, Inc.
    Inventors: Malav Parikh, Sergio Schuler, Vimal Reddy, Zainab Zaidi, Paul Toth, Adam Caughron, Bryant Sorensen, Alex Dang-Tran, Scott Johnson, Raul Garibay, Andrew Morten, David Fick
  • Patent number: 10977339
    Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: April 13, 2021
    Assignee: Mythic, Inc.
    Inventors: David Fick, Michael Henry, Laura Fick, Malav Parikh, Skylar Skrzyniarz, Scott Johnson, Pei-Ci Wu, Andrew Morten
  • Patent number: 10929748
    Abstract: Systems and methods for improving a computational performance of a mixed-signal integrated circuit includes identifying a suboptimal graph component of a computation graph of a subject application, wherein: (i) the computation graph comprises a plurality of graphical nodes representing computational operations and a plurality of graphical edges representing data dependencies between the graphical nodes, and (ii) the suboptimal graph component comprises a subset of the plurality of graphical nodes and the plurality of graphical edges that do not satisfy an optimal operation threshold; at compile time, selectively applying an optimizing transformation to the suboptimal graph component based on attributes of a first activation function within the suboptimal graph component, wherein the optimization transformation, when applied, transforms the suboptimal graph component to an optimal graph component that satisfies the optimal operation threshold; and reconstructing the computation graph using the optimal graph co
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: February 23, 2021
    Assignee: Mythic, Inc.
    Inventors: Andrew Morten, Eric Stotzer, Pei-Ci Wu, Michail Tzoufras, David Fick
  • Publication number: 20200081937
    Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.
    Type: Application
    Filed: November 14, 2019
    Publication date: March 12, 2020
    Inventors: David Fick, Michael Henry, Laura Fick, Malav Parikh, Skylar Skrzyniarz, Scott Johnson, Pei-Ci Wu, Andrew Morten
  • Patent number: 10515136
    Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: December 24, 2019
    Assignee: Mythic, Inc.
    Inventors: David Fick, Michael Henry, Laura Fick, Malav Parikh, Skylar Skrzyniarz, Scott Johnson, Pei-Ci Wu, Andrew Morten