Patents by Inventor Andrew N. Westmeyer

Andrew N. Westmeyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8426858
    Abstract: Some embodiments of the present invention include providing carbon doped regions and raised source/drain regions to provide tensile stress in NMOS transistor channels.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: April 23, 2013
    Assignee: Intel Corporation
    Inventors: Michael L. Hattendorf, Jack Hwang, Anand Murthy, Andrew N. Westmeyer
  • Publication number: 20110068403
    Abstract: Some embodiments of the present invention include providing carbon doped regions and raised source/drain regions to provide tensile stress in NMOS transistor channels.
    Type: Application
    Filed: November 30, 2010
    Publication date: March 24, 2011
    Inventors: Michael L. Hattendorf, Jack Hwang, Anand Murthy, Andrew N. Westmeyer
  • Patent number: 7858981
    Abstract: Some embodiments of the present invention include providing carbon doped regions and raised source/drain regions to provide tensile stress in NMOS transistor channels.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: December 28, 2010
    Assignee: Intel Corporation
    Inventors: Michael L. Hattendorf, Jack Hwang, Anand Murthy, Andrew N. Westmeyer
  • Patent number: 7812394
    Abstract: This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent deposition in the same reactor without atmospheric exposure. In-situ etching of the source-drain recess for replacement source-drain applications provides several advantages over state of the art ex-situ etching. Transistor drive current is improved by: (1) Eliminating contamination of the silicon-epilayer interface when the as-etched surface is exposed to atmosphere and (2) Precise control over the shape of the etch recess. Deposition may be done by a variety of techniques including selective and non-selective methods. In the case of blanket deposition, a measure to avoid amorphous deposition in performance critical regions is also presented.
    Type: Grant
    Filed: October 13, 2008
    Date of Patent: October 12, 2010
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Glenn A. Glass, Andrew N. Westmeyer, Michael L. Hattendorf, Jeffrey R. Wank
  • Publication number: 20090152601
    Abstract: Some embodiments of the present invention include providing carbon doped regions and raised source/drain regions to provide tensile stress in NMOS transistor channels.
    Type: Application
    Filed: January 12, 2009
    Publication date: June 18, 2009
    Inventors: Michael L. Hattendorf, Jack Hwang, Anand Murthy, Andrew N. Westmeyer
  • Publication number: 20090039390
    Abstract: This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent deposition in the same reactor without atmospheric exposure. In-situ etching of the source-drain recess for replacement source-drain applications provides several advantages over state of the art ex-situ etching. Transistor drive current is improved by: (1) Eliminating contamination of the silicon-epilayer interface when the as-etched surface is exposed to atmosphere and (2) Precise control over the shape of the etch recess. Deposition may be done by a variety of techniques including selective and non-selective methods. In the case of blanket deposition, a measure to avoid amorphous deposition in performance critical regions is also presented.
    Type: Application
    Filed: October 13, 2008
    Publication date: February 12, 2009
    Inventors: Anand Murthy, Glenn A. Glass, Andrew N. Westmeyer, Michael L. Hattendorf, Jeffrey R. Wank
  • Patent number: 7479431
    Abstract: Some embodiments of the present invention include providing carbon doped regions and raised source/drain regions to provide tensile stress in NMOS transistor channels.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: January 20, 2009
    Assignee: Intel Corporation
    Inventors: Michael L. Hattendorf, Jack Hwang, Anand Murthy, Andrew N. Westmeyer
  • Patent number: 7479432
    Abstract: This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent deposition in the same reactor without atmospheric exposure. In-situ etching of the source-drain recess for replacement source-drain applications provides several advantages over state of the art ex-situ etching. Transistor drive current is improved by: (1) Eliminating contamination of the silicon-epilayer interface when the as-etched surface is exposed to atmosphere and (2) Precise control over the shape of the etch recess. Deposition may be done by a variety of techniques including selective and non-selective methods. In the case of blanket deposition, a measure to avoid amorphous deposition in performance critical regions is also presented.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: January 20, 2009
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Glenn A. Glass, Andrew N. Westmeyer, Michael L. Hattendorf, Jeffrey R. Wank
  • Patent number: 7427775
    Abstract: The mobility of carriers may be increased in strained channel epitaxial source/drain transistors. Doped silicon material may be blanket deposited after removing ion implanted source/drain regions. The blanket deposition forms amorphous films over non-source/drain areas and crystalline films in source/drain regions. By using an etch which is selective to amorphous silicon, the amorphous material may be removed. This may avoid some problems associated with selective deposition of the doped silicon material.
    Type: Grant
    Filed: April 24, 2007
    Date of Patent: September 23, 2008
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Justin K. Brask, Andrew N. Westmeyer, Boyan Boyanov, Nick Lindert
  • Patent number: 7402872
    Abstract: A method is described for manufacturing an n-MOS semiconductor transistor. Recesses are formed in a semiconductor substrate adjacent a gate electrode structure. Silicon is embedded in the recesses via a selective epitaxial growth process. The epitaxial silicon is in-situ alloyed with substitutional carbon and in-situ doped with phosphorus. The silicon-carbon alloy generates a uniaxial tensile strain in the channel region between the source and drain, thereby increasing electron channel mobility and the transistor's drive current. The silicon-carbon alloy decreases external resistances by reducing contact resistance between source/drain and silicide regions and by reducing phosphorous diffusivity, thereby permitting closer placement of the transistor's source/drain and channel regions.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: July 22, 2008
    Assignee: Intel Corporation
    Inventors: Anand S. Murthy, Glenn A. Glass, Andrew N. Westmeyer, Michael L. Hattendorf, Tahir Ghani
  • Patent number: 7226842
    Abstract: The mobility of carriers may be increased in strained channel epitaxial source/drain transistors. Doped silicon material may be blanket deposited after removing ion implanted source/drain regions. The blanket deposition forms amorphous films over non-source/drain areas and crystalline films in source/drain regions. By using an etch which is selective to amorphous silicon, the amorphous material may be removed. This may avoid some problems associated with selective deposition of the doped silicon material.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: June 5, 2007
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Justin K. Brask, Andrew N. Westmeyer, Boyan Boyanov, Nick Lindert
  • Patent number: 7195985
    Abstract: This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent deposition in the same reactor without atmospheric exposure. In-situ etching of the source-drain recess for replacement source-drain applications provides several advantages over state of the art ex-situ etching. Transistor drive current is improved by: (1) Eliminating contamination of the silicon-epilayer interface when the as-etched surface is exposed to atmosphere and (2) Precise control over the shape of the etch recess. Deposition may be done by a variety of techniques including selective and non-selective methods. In the case of blanket deposition, a measure to avoid amorphous deposition in performance critical regions is also presented.
    Type: Grant
    Filed: January 4, 2005
    Date of Patent: March 27, 2007
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Glenn A. Glass, Andrew N. Westmeyer, Michael L. Hattendorf, Jeffrey R. Wank