Patents by Inventor Andrew Nathan Mort

Andrew Nathan Mort has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12191864
    Abstract: A multiple operating-mode comparator system can be useful for high bandwidth and low power automated testing. The system can include a gain stage configured to drive a high impedance input of a comparator output stage, wherein the gain stage includes a differential switching stage coupled to an adjustable impedance circuit, and an impedance magnitude characteristic of the adjustable impedance circuit corresponds to a bandwidth characteristic of the gain stage. The comparator output stage can include a buffer circuit coupled to a low impedance comparator output node. The buffer circuit can provide a reference voltage for a switched output signal at the output node in a higher speed mode, and the buffer circuit can provide the switched output signal at the output node in a lower power mode.
    Type: Grant
    Filed: March 20, 2023
    Date of Patent: January 7, 2025
    Assignee: Analog Devices, Inc.
    Inventors: Christopher C. McQuilkin, Andrew Nathan Mort
  • Publication number: 20230231547
    Abstract: A multiple operating-mode comparator system can be useful for high bandwidth and low power automated testing. The system can include a gain stage configured to drive a high impedance input of a comparator output stage, wherein the gain stage includes a differential switching stage coupled to an adjustable impedance circuit, and an impedance magnitude characteristic of the adjustable impedance circuit corresponds to a bandwidth characteristic of the gain stage. The comparator output stage can include a buffer circuit coupled to a low impedance comparator output node. The buffer circuit can provide a reference voltage for a switched output signal at the output node in a higher speed mode, and the buffer circuit can provide the switched output signal at the output node in a lower power mode.
    Type: Application
    Filed: March 20, 2023
    Publication date: July 20, 2023
    Inventors: Christopher C. McQuilkin, Andrew Nathan Mort
  • Patent number: 11686773
    Abstract: A test system can receive a test signal from a device under test (DUI) via a first signal path. A comparator circuit can receive the test signal and, in response, generate an intermediate output signal based on a magnitude relationship between the test signal a comparator reference signal. A compensation circuit can generate a correction signal that is complementary to a portion of the received test signal, such as to correct for loading effects of the first signal path. The test system can include an output circuit configured to provide a corrected differential output signal that is based on a combination of the intermediate output signal and the correction signal.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: June 27, 2023
    Assignee: Analog Devices, Inc.
    Inventors: Christopher C. McQuilkin, Andrew Nathan Mort
  • Patent number: 11637551
    Abstract: A multiple operating-mode comparator system can be useful for high bandwidth and low power automated testing. The system can include a gain stage configured to drive a high impedance input of a comparator output stage, wherein the gain stage includes a differential switching stage coupled to an adjustable impedance circuit, and an impedance magnitude characteristic of the adjustable impedance circuit corresponds to a bandwidth characteristic of the gain stage. The comparator output stage can include a buffer circuit coupled to a low impedance comparator output node. The buffer circuit can provide a reference voltage for a switched output signal at the output node in a higher speed mode, and the buffer circuit can provide the switched output signal at the output node in a lower power mode.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: April 25, 2023
    Assignee: Analog Devices, Inc.
    Inventors: Christopher C. McQuilkin, Andrew Nathan Mort
  • Publication number: 20220311426
    Abstract: A deskew system can be used to adjust signal characteristics such as pulse width and edge timing. In an example, a deskew system can include multiple timing control cells and each cell can operate in one of multiple different modes according to respective mode control signals. The modes can include at least a signal delay mode and a signal pulse width adjustment mode. In an example, a first cell in a deskew system can be configured to receive a test input signal at a first input node and, in response, provide a deskew output signal at a first output node. The deskew output signal can be based on the test input signal, a pulse width adjustment provided by the first cell, and on a delayed signal, corresponding to the input signal, that is provided by a subsequent cell in the series.
    Type: Application
    Filed: March 26, 2021
    Publication date: September 29, 2022
    Inventor: Andrew Nathan Mort
  • Patent number: 11456729
    Abstract: A deskew system can be used to adjust signal characteristics such as pulse width and edge timing. In an example, a deskew system can include multiple timing control cells and each cell can operate in one of multiple different modes according to respective mode control signals. The modes can include at least a signal delay mode and a signal pulse width adjustment mode. In an example, a first cell in a deskew system can be configured to receive a test input signal at a first input node and, in response, provide a deskew output signal at a first output node. The deskew output signal can be based on the test input signal, a pulse width adjustment provided by the first cell, and on a delayed signal, corresponding to the input signal, that is provided by a subsequent cell in the series.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: September 27, 2022
    Assignee: Analog Devices, Inc.
    Inventor: Andrew Nathan Mort
  • Publication number: 20210391854
    Abstract: A multiple operating-mode comparator system can be useful for high bandwidth and low power automated testing. The system can include a gain stage configured to drive a high impedance input of a comparator output stage, wherein the gain stage includes a differential switching stage coupled to an adjustable impedance circuit, and an impedance magnitude characteristic of the adjustable impedance circuit corresponds to a bandwidth characteristic of the gain stage. The comparator output stage can include a buffer circuit coupled to a low impedance comparator output node. The buffer circuit can provide a reference voltage for a switched output signal at the output node in a higher speed mode, and the buffer circuit can provide the switched output signal at the output node in a lower power mode.
    Type: Application
    Filed: August 30, 2021
    Publication date: December 16, 2021
    Inventors: Christopher C. McQuilkin, Andrew Nathan Mort
  • Publication number: 20210297069
    Abstract: A multiple operating-mode comparator system can be useful for high bandwidth and low power automated testing. The system can include a gain stage configured to drive a high impedance input of a comparator output stage, wherein the gain stage includes a differential switching stage coupled to an adjustable impedance circuit, and an impedance magnitude characteristic of the adjustable impedance circuit corresponds to a bandwidth characteristic of the gain stage. The comparator output stage can include a buffer circuit coupled to a low impedance comparator output node. The buffer circuit can provide a reference voltage for a switched output signal at the output node in a higher speed mode, and the buffer circuit can provide the switched output signal at the output node in a lower power mode.
    Type: Application
    Filed: March 23, 2020
    Publication date: September 23, 2021
    Inventors: Christopher C. McQuilkin, Andrew Nathan Mort
  • Patent number: 11128287
    Abstract: A multiple operating-mode comparator system can be useful for high bandwidth and low power automated testing. The system can include a gain stage configured to drive a high impedance input of a comparator output stage, wherein the gain stage includes a differential switching stage coupled to an adjustable impedance circuit, and an impedance magnitude characteristic of the adjustable impedance circuit corresponds to a bandwidth characteristic of the gain stage. The comparator output stage can include a buffer circuit coupled to a low impedance comparator output node. The buffer circuit can provide a reference voltage for a switched output signal at the output node in a higher speed mode, and the buffer circuit can provide the switched output signal at the output node in a lower power mode.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: September 21, 2021
    Assignee: Analog Devices, Inc.
    Inventors: Christopher C. McQuilkin, Andrew Nathan Mort
  • Patent number: 10547294
    Abstract: This disclosure is in the field of electronics and more specifically in the field of timing control electronics. In an example, a timing control system can include or use an array of circuit cells, and each cell can provide a signal delay using a fixed delay or interpolation. The interpolation can include, in one or more cells, using three timing signals with substantially different delays to create a delayed output signal. Linearity of the delayed output signal is thereby improved. In an example, an impedance transformation circuit can be applied to improve a bandwidth in one or more of the cells to thereby improve the bandwidth of the timing control system.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: January 28, 2020
    Assignee: Analog Devices, Inc.
    Inventors: Andrew Nathan Mort, Christopher C. McQuilkin
  • Publication number: 20180358957
    Abstract: This disclosure is in the field of electronics and more specifically in the field of timing control electronics. In an example, a timing control system can include or use an array of circuit cells, and each cell can provide a signal delay using a fixed delay or interpolation. The interpolation can include, in one or more cells, using three timing signals with substantially different delays to create a delayed output signal. Linearity of the delayed output signal is thereby improved. In an example, an impedance transformation circuit can be applied to improve a bandwidth in one or more of the cells to thereby improve the bandwidth of the timing control system.
    Type: Application
    Filed: June 9, 2017
    Publication date: December 13, 2018
    Inventors: Andrew Nathan Mort, Christopher C. McQuilkin