Abstract: Methods, a system and software for simulating the operation of a data processing apparatus to determine timing information of data transfers are provided. The data processing apparatus comprises a number of master logic units and slave logic units coupled via a bus, the data processing apparatus is operable to perform the data transfers between the master logic units and the slave logic units over the bus.

Abstract: An apparatus, method and computer program product are provided for performing a sequence of verification tests to perform hardware and software co-verification on a system under verification. The apparatus comprises a plurality of signal interface controllers operable to be coupled to the system under verification, with each signal interface controller being operable to perform one or more test actions transferring at least one of one or more stimulus signals and one or more response signals between a corresponding portion of the system under verification and the signal interface controller during performance of the sequence of verification tests. A debugger is also provided which is operable to control operation of a processing unit associated with the system under verification, the processing unit being operable to execute software routines.