Patents by Inventor Andrew Ott

Andrew Ott has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Transistor having an etch stop layer including a metal compound that is selectively formed over a metal gate, and method therefor
    Patent number: 8399317
    Abstract: In one aspect, an apparatus may include a metal gate of a transistor. An etch stop layer may be selectively formed over the metal gate. The etch stop layer may include a metal compound. An insulating layer may be over the etch stop layer. A conductive structure may be included through the insulating layer to the metal gate. Methods of making such transistors are also disclosed.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: March 19, 2013
    Assignee: Intel Corporation
    Inventors: Andrew Ott, Sean King, Ajay Sharma
  • Transistor having an etch stop layer including a metal compound that is selectively formed over a metal gate
    Patent number: 8120114
    Abstract: In one aspect, an apparatus may include a metal gate of a transistor. An etch stop layer may be selectively formed over the metal gate. The etch stop layer may include a metal compound. An insulating layer may be over the etch stop layer. A conductive structure may be included through the insulating layer to the metal gate. Methods of making such transistors are also disclosed.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: February 21, 2012
    Assignee: Intel Corporation
    Inventors: Andrew Ott, Sean King, Ajay Sharma
  • TRANSISTOR HAVING AN ETCH STOP LAYER INCLUDING A METAL COMPOUND THAT IS SELECTIVELY FORMED OVER A METAL GATE, AND METHOD THEREFOR
    Publication number: 20120034773
    Abstract: In one aspect, an apparatus may include a metal gate of a transistor. An etch stop layer may be selectively formed over the metal gate. The etch stop layer may include a metal compound. An insulating layer may be over the etch stop layer. A conductive structure may be included through the insulating layer to the metal gate. Methods of making such transistors are also disclosed.
    Type: Application
    Filed: October 14, 2011
    Publication date: February 9, 2012
    Inventors: Andrew Ott, Sean King, Ajay Sharma
  • Transistor having an etch stop layer including a metal compound that is selectively formed over a metal gate, and method therefor
    Publication number: 20080157365
    Abstract: In one aspect, an apparatus may include a metal gate of a transistor. An etch stop layer may be selectively formed over the metal gate. The etch stop layer may include a metal compound. An insulating layer may be over the etch stop layer. A conductive structure may be included through the insulating layer to the metal gate. Methods of making such transistors are also disclosed.
    Type: Application
    Filed: December 27, 2006
    Publication date: July 3, 2008
    Inventors: Andrew Ott, Sean King, Ajay Sharma
  • Method of making semiconductor device using a novel interconnect cladding layer
    Patent number: 7214594
    Abstract: A method and apparatus are provided an interconnect cladding layer. In one embodiment, a first sacrificial layer is deposited over a substrate and patterned. In the vias created during the patterning operation, a conductive material is placed to create conductive interconnects. After planarizing the conductive material, the sacrificial layer is removed leaving the interconnect exposed. A cladding layer is then deposited over the conductive material.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: May 8, 2007
    Assignee: Intel Corporation
    Inventors: Lawrence D. Wong, Jihperng Leu, Grant Kloster, Andrew Ott, Patrick Morrow
  • Forming a dielectric layer using a hydrocarbon-containing precursor
    Publication number: 20070032675
    Abstract: In one embodiment, the present invention includes introducing a precursor containing hydrocarbon substituents and optionally a second conventional or hydrocarbon-containing precursor into a vapor deposition apparatus; and forming a dielectric layer having the hydrocarbon substituents on a substrate within the vapor deposition apparatus from the precursor(s). In certain embodiments, at least a portion of the hydrocarbon substituents may be later removed from the dielectric layer to reduce density thereof.
    Type: Application
    Filed: October 13, 2006
    Publication date: February 8, 2007
    Inventors: Robert Meagley, Michael Goodner, Andrew Ott, Grant Kloster, Michael McSwiney, Bob Leet
  • Structure in a microelectronic device including a bi-layer for a diffusion barrier and an etch-stop layer
    Patent number: 7164206
    Abstract: The invention relates to a microelectronic device and a structure therein that includes a diffusion barrier layer having a first thickness and a first dielectric constant. An etch stop layer is disposed above and on the diffusion barrier layer. The etch stop layer has a second thickness and a second dielectric constant.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: January 16, 2007
    Assignee: Intel Corporation
    Inventors: Grant Kloster, Jihperng Leu, Lawrence Wong, Andrew Ott, Patrick Marrow
  • INTEGRATED LOW-K HARD MASK
    Publication number: 20060038296
    Abstract: Embodiments of the invention provide a device with a hard mask layer between first and second ILD layers. The hard mask layer may have a k value approximately equal to the first and/or second ILD layers.
    Type: Application
    Filed: January 3, 2005
    Publication date: February 23, 2006
    Inventors: Sean King, Andrew Ott
  • Dual-damascene interconnects without an etch stop layer by alternating ILDs
    Patent number: 6992391
    Abstract: A dual-damascene process where first alternate ILDs are made of a first material and second alternate ILDs are made of a second material. Each material is etchable at a faster rate than the other in the presence of different etchant such as for an organic polymer and an inorganic low k material. This allows the ILDs to be deposited alternately on one another without an etchant stop layer thereby reducing capacitance.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: January 31, 2006
    Assignee: Intel Corporation
    Inventors: Andrew Ott, Lawrence Wong, Patrick Morrow, Jihperng Leu, Grant M. Kloster
  • Dual-damascene interconnects without an etch stop layer by alternating ILDs
    Publication number: 20050208753
    Abstract: A dual-damascene process where first alternate ILDs are made of a first material and second alternate ILDs are made of a second material. Each material is etchable at a faster rate than the other in the presence of different etchant such as for an organic polymer and an inorganic low k material. This allows the ILDs to be deposited alternately on one another without an etchant stop layer thereby reducing capacitance.
    Type: Application
    Filed: May 17, 2005
    Publication date: September 22, 2005
    Inventors: Andrew Ott, Lawrence Wong, Patrick Morrow, Jihperng Leu, Grant Kloster
  • Adhesion between carbon doped oxide and etch stop layers
    Publication number: 20050087517
    Abstract: The invention forms a graded modified layer in a substrate by exposing the substrate to hydrogen plasma. Methyl groups may be removed from carbon doped oxide in the substrate by the hydrogen plasma treatment. This may result in a stronger interface between the substrate and an etch stop layer on the substrate.
    Type: Application
    Filed: October 9, 2003
    Publication date: April 28, 2005
    Inventors: Andrew Ott, Ajay Jain, Ying Zhou, Jessica Xu
  • Method of operating a processing chamber having multiple stations
    Patent number: 6645877
    Abstract: A method for operating a multi-station processing chamber is described. A wafer is loaded onto the first station then indexed to the second station prior to processing. The indexing causes the wafer to be well-seated on it spindle before being processed. This prevents an improperly seated wafer from being processed at the first station.
    Type: Grant
    Filed: January 28, 2002
    Date of Patent: November 11, 2003
    Assignee: Intel Corporation
    Inventors: Andrew Ott, Jennifer L. O'Loughlin
  • Method of making semiconductor device using a novel interconnect cladding layer
    Publication number: 20030186535
    Abstract: A method and apparatus are provided an interconnect cladding layer. In one embodiment, a first sacrificial layer is deposited over a substrate and patterned. In the vias created during the patterning operation, a conductive material is placed to create conductive interconnects. After planarizing the conductive material, the sacrificial layer is removed leaving the interconnect exposed. A cladding layer is then deposited over the conductive material.
    Type: Application
    Filed: March 26, 2002
    Publication date: October 2, 2003
    Inventors: Lawrence D. Wong, Jihperng Leu, Grant Kloster, Andrew Ott, Patrick Morrow
  • Method of making a semiconductor device using a damascene interconnect with a laminated dielectric
    Publication number: 20030173651
    Abstract: A method of fabricating a semiconductor device includes laminating a dielectric sheet on a substrate and forming a via opening in the dielectric sheet. The method further includes depositing a conductive material into the first via opening.
    Type: Application
    Filed: March 15, 2002
    Publication date: September 18, 2003
    Inventors: Lawrence D. Wong, Jihperng Leu, Grant Kloster, Andrew Ott, Patrick Morrow
  • Method of operating a processing chamber having multiple stations
    Publication number: 20030143823
    Abstract: A method for operating a multi-station processing chamber is described. A wafer is loaded onto the first station then indexed to the second station prior to processing. The indexing causes the wafer to be well-seated on it spindle before being processed. This prevents an improperly seated wafer from being processed at the first station.
    Type: Application
    Filed: January 28, 2002
    Publication date: July 31, 2003
    Inventors: Andrew Ott, Jennifer L. O'Loughlin
  • Dual-damascene interconnects without an etch stop layer by alternating ILDs
    Publication number: 20030064580
    Abstract: A dual-damascene process where first alternate ILDs are made of a first material and second alternate ILDs are made of a second material. Each material is etchable at a faster rate than the other in the presence of different etchant such as for an organic polymer and an inorganic low k material. This allows the ILDs to be deposited alternately on one another without an etchant stop layer thereby reducing capacitance.
    Type: Application
    Filed: September 28, 2001
    Publication date: April 3, 2003
    Inventors: Andrew Ott, Lawrence Wong, Patrick Morrow, Jihperng Leu, Grant M. Kloster
  • Structure in a microelectronic device including a bi-layer for a diffusion barrier and an etch-stop layer
    Publication number: 20020140103
    Abstract: The invention relates to a microelectronic device and a structure therein that includes a diffusion barrier layer having a first thickness and a first dielectric constant. An etch stop layer is disposed above and on the diffusion barrier layer. The etch stop layer has a second thickness and a second dielectric constant.
    Type: Application
    Filed: March 28, 2001
    Publication date: October 3, 2002
    Inventors: Grant Kloster, Jihperng Leu, Lawrence Wong, Andrew Ott, Patrick Morrow