Patents by Inventor Andrew P. Collins
Andrew P. Collins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230299044Abstract: In one embodiment, a multi-die complex includes a mold material, first and second integrated circuit dies within the mold material, and one or more metal layers within the mold material. One or more passive electrical components, e.g., an inductor, a capacitor, or RF shielding, are formed at least partially within the metal layers.Type: ApplicationFiled: March 18, 2022Publication date: September 21, 2023Applicant: Intel CorporationInventors: Andrew P. Collins, Arghya Sain, Sujit Sharan, Jianyong Xie
-
Publication number: 20230207494Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a first layer that comprises glass. In an embodiment, a second layer comprising glass is over the first layer. In an embodiment, the electronic package further comprises an inductor between the first layer and the second layer.Type: ApplicationFiled: December 24, 2021Publication date: June 29, 2023Inventors: Jianyong XIE, Andrew P. COLLINS, Arghya SAIN, Sivaseetharaman PANDI, Telesphor KAMGAING
-
Publication number: 20230207406Abstract: Embodiments disclosed herein include a package core. In an embodiment, the package core includes a first layer, where the first layer comprises glass. In an embodiment, a second layer is over the first layer, where the second layer comprises glass. In an embodiment, a third layer is over the second layer, where the third layer comprises glass. In an embodiment, a first trace is between the first layer and the second layer. In an embodiment, a second trace is between the second layer and the third layer.Type: ApplicationFiled: December 24, 2021Publication date: June 29, 2023Inventors: Arghya SAIN, Andrew P. COLLINS, Sivaseetharaman PANDI, Jianyong XIE, Telesphor KAMGAING
-
Publication number: 20230207405Abstract: Embodiments disclosed herein include electronic devices. In an embodiment, an electronic device comprises a core, where the core comprises a first layer comprising glass, and a second layer comprising glass over the first layer. In an embodiment, a trace is between the first layer and the second layer. In an embodiment, routing layers are on the core.Type: ApplicationFiled: December 24, 2021Publication date: June 29, 2023Inventors: Arghya SAIN, Andrew P. COLLINS, Sivaseetharaman PANDI, Telesphor KAMGAING, Tolga ACIKALIN, Shuhei YAMADA
-
Publication number: 20230197646Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass. In an embodiment, the electronic package further comprises a trace embedded in the substrate, where a width of the trace is less than a height of the trace. In an embodiment, the electronic package further comprises a first layer on the first surface of the substrate, where the first layer is a dielectric buildup film, and a second layer on the second surface of the substrate, where the second layer is the dielectric buildup film.Type: ApplicationFiled: December 21, 2021Publication date: June 22, 2023Inventors: Aleksandar ALEKSOV, Telesphor KAMGAING, Georgios C. DOGIAMIS, Neelam PRABHU GAUNKAR, Veronica STRONG, Brandon RAWLINGS, Andrew P. COLLINS, Arghya SAIN, Sivaseetharaman PANDI
-
Publication number: 20230197593Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a core, where the core comprises glass, and a first via through the core. In an embodiment, a first fin extends out laterally from the first via. In an embodiment, the electronic package further comprises a second via through the core, and a second fin extending out laterally from the second via. In an embodiment, a face of the first fin overlaps a face of the second fin.Type: ApplicationFiled: December 16, 2021Publication date: June 22, 2023Inventors: Sivaseetharaman PANDI, Andrew P. COLLINS, Arghya SAIN, Telesphor KAMGAING
-
Publication number: 20230197592Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a core with a first surface and a second surface, where the core comprises glass. In an embodiment, a first buildup layer is over the first surface of the core, and a second buildup layer is under the second surface of the core. In an embodiment, the electronic package further comprises a via through the core between the first surface of the core and the second surface of the core, and a plane into the first surface of the core, where a width of the plane is greater than a width of the via.Type: ApplicationFiled: December 16, 2021Publication date: June 22, 2023Inventors: Telesphor KAMGAING, Brandon RAWLINGS, Aleksandar ALEKSOV, Andrew P. COLLINS, Georgios C. DOGIAMIS, Veronica STRONG, Neelam PRABHU GAUNKAR
-
Publication number: 20230138386Abstract: Systems and methods of conductively coupling at least three semiconductor dies included in a semiconductor package using a multi-die interconnect bridge that is embedded, disposed, or otherwise integrated into the semiconductor package substrate are provided. The multi-die interconnect bridge is a passive device that includes passive electronic components such as conductors, resistors, capacitors and inductors. The multi-die interconnect bridge communicably couples each of the semiconductor dies included in the at least three semiconductor dies to each of at least some of the remaining at least three semiconductor dies. The multi-die interconnect bridge occupies a first area on the surface of the semiconductor package substrate. The smallest of the at least three semiconductor dies coupled to the multi-die interconnect bridge 120 occupies a second area on the surface of the semiconductor package substrate, where the second area is greater than the first area.Type: ApplicationFiled: December 20, 2022Publication date: May 4, 2023Applicant: Intel CorporationInventors: ANDREW P. COLLINS, DIGVIJAY A. RAORANE, WILFRED GOMES, RAVINDRANATH V. MAHAJAN, SUJIT SHARAN
-
Patent number: 11569173Abstract: Systems and methods of conductively coupling at least three semiconductor dies included in a semiconductor package using a multi-die interconnect bridge that is embedded, disposed, or otherwise integrated into the semiconductor package substrate are provided. The multi-die interconnect bridge is a passive device that includes passive electronic components such as conductors, resistors, capacitors and inductors. The multi-die interconnect bridge communicably couples each of the semiconductor dies included in the at least three semiconductor dies to each of at least some of the remaining at least three semiconductor dies. The multi-die interconnect bridge occupies a first area on the surface of the semiconductor package substrate. The smallest of the at least three semiconductor dies coupled to the multi-die interconnect bridge 120 occupies a second area on the surface of the semiconductor package substrate, where the second area is greater than the first area.Type: GrantFiled: December 29, 2017Date of Patent: January 31, 2023Assignee: Intel CorporationInventors: Andrew P. Collins, Digvijay A. Raorane, Wilfred Gomes, Ravindranath V. Mahajan, Sujit Sharan
-
Patent number: 11462521Abstract: A package is disclosed. The package includes a base die. The base die includes voltage regulating circuitry and input and output (I/O) circuitry. The I/O circuitry surrounds the voltage regulating circuitry. The package also includes a top set of dies. The top set of dies includes a plurality of dies that include logic circuitry and a plurality of dies that include passive components. The plurality of dies that include passive components surround the plurality of dies that include logic circuitry. The plurality of dies that includes passive components is coupled to the logic circuitry and to the voltage regulating circuitry.Type: GrantFiled: June 28, 2018Date of Patent: October 4, 2022Assignee: Intel CorporationInventors: Andrew P. Collins, Jianyong Xie, Sujit Sharan
-
Publication number: 20200006302Abstract: A package is disclosed. The package includes a base die. The base die includes voltage regulating circuitry and input and output (I/O) circuitry. The I/O circuitry surrounds the voltage regulating circuitry. The package also includes a top set of dies. The top set of dies includes a plurality of dies that include logic circuitry and a plurality of dies that include passive components. The plurality of dies that include passive components surround the plurality of dies that include logic circuitry. The plurality of dies that includes passive components is coupled to the logic circuitry and to the voltage regulating circuitry.Type: ApplicationFiled: June 28, 2018Publication date: January 2, 2020Inventors: Andrew P. Collins, Jianyong Xie, Sujit Sharan
-
Patent number: 10518525Abstract: Techniques are disclosed for connecting a printing plate to a print cylinder or surface. The techniques may be implemented, for instance, with respect to a printing plate, a print cylinder, a print sleeve, or some combination thereof. In an embodiment, a field of mechanical fasteners is provisioned on a printing plate, and a complementary field of mechanical fasteners is provisioned on a print sleeve or cylinder. The mechanical fasteners collectively operate to provide a mechanical bond or interface that inhibits lateral and rotational movement of the plate during printing operations, and can also be configured to manage backlash between engaging surfaces of the interface. In some cases, backlash management includes use of cushion effect integral with the mechanical bond itself and/or unidirectional and possibly angled fastener elements to provide a snugging effect.Type: GrantFiled: July 10, 2015Date of Patent: December 31, 2019Assignee: VELCRO BVBAInventors: Luis Parellada Armela, Josep M. Soler Carbonell, Mark A. Clarner, Andrew P. Collins, Paul R. Erickson, Christopher M. Gallant, David Villeneuve
-
Publication number: 20190206798Abstract: Systems and methods of conductively coupling at least three semiconductor dies included in a semiconductor package using a multi-die interconnect bridge that is embedded, disposed, or otherwise integrated into the semiconductor package substrate are provided. The multi-die interconnect bridge is a passive device that includes passive electronic components such as conductors, resistors, capacitors and inductors. The multi-die interconnect bridge communicably couples each of the semiconductor dies included in the at least three semiconductor dies to each of at least some of the remaining at least three semiconductor dies. The multi-die interconnect bridge occupies a first area on the surface of the semiconductor package substrate. The smallest of the at least three semiconductor dies coupled to the multi-die interconnect bridge 120 occupies a second area on the surface of the semiconductor package substrate, where the second area is greater than the first area.Type: ApplicationFiled: December 29, 2017Publication date: July 4, 2019Applicant: Intel CorporationInventors: ANDREW P. COLLINS, DIGVIJAY A. RAORANE, WILFRED GOMES, RAVINDRANATH V. MAHAJAN, SUJIT SHARAN
-
Publication number: 20180270948Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.Type: ApplicationFiled: August 14, 2017Publication date: September 20, 2018Applicant: Intel CorporationInventors: William L. Barber, Keith Pinson, Andrew P. Collins, Boping Wu, Isaac Ali, Colin L. Perry
-
Patent number: 10015878Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.Type: GrantFiled: November 19, 2015Date of Patent: July 3, 2018Assignee: INTEL CORPORATIONInventors: William L. Barber, Keith Pinson, Andrew P. Collins, Boping Wu, Isaac Ali, Colin L. Perry
-
Publication number: 20170217157Abstract: Techniques are disclosed for connecting a printing plate to a print cylinder or surface. The techniques may be implemented, for instance, with respect to a printing plate, a print cylinder, a print sleeve, or some combination thereof. In an embodiment, a field of mechanical fasteners is provisioned on a printing plate, and a complementary field of mechanical fasteners is provisioned on a print sleeve or cylinder. The mechanical fasteners collectively operate to provide a mechanical bond or interface that inhibits lateral and rotational movement of the plate during printing operations, and can also be configured to manage backlash between engaging surfaces of the interface. In some cases, backlash management includes use of cushion effect integral with the mechanical bond itself and/or unidirectional and possibly angled fastener elements to provide a snugging effect.Type: ApplicationFiled: July 10, 2015Publication date: August 3, 2017Applicant: Velcro BVBAInventors: LUIS PARELLADA ARMELA, JOSEP M. SOLER CARBONELL, MARK A. CLARNER, ANDREW P. COLLINS, PAUL R. ERICKSON, CHRISTOPHER M. GALLANT, DAVID VILLENEUVE
-
Publication number: 20160309580Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.Type: ApplicationFiled: November 19, 2015Publication date: October 20, 2016Applicant: INTEL CORPORATIONInventors: William L. Barber, Keith Pinson, Andrew P. Collins, Boping Wu, Isaac Ali, Colin L. Perry
-
Patent number: 9225164Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.Type: GrantFiled: November 6, 2014Date of Patent: December 29, 2015Assignee: INTEL CORPORATIONInventors: William L. Barber, Keith Pinson, Andrew P. Collins, Boping Wu, Isaac Ali, Colin L. Perry
-
Publication number: 20150131190Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.Type: ApplicationFiled: November 6, 2014Publication date: May 14, 2015Inventors: William L. Barber, Keith Pinson, Andrew P. Collins, Boping Wu, Isaac Ali, Colin L. Perry
-
Patent number: 8913364Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.Type: GrantFiled: December 20, 2011Date of Patent: December 16, 2014Assignee: Intel CorporationInventors: William L. Barber, Keith Pinson, Andrew P. Collins, Boping Wu, Isaac Ali, Colin L. Perry