Abstract: According to one general aspect, a method may include receiving a data file that includes placement data regarding a plurality of circuit cells. The circuit cells may include respective layout portions. The layout portions may be associated with a plurality of respective lithographic colors. The method may include determining if a violating circuit cell is to be re-colored. The method may include indicating that, via at least one shape on a color swap layer in the data file, the violating circuit cell is to be at least partially re-colored. A color swap layer shape may cause a mask generator to re-color the portion of the violating circuit cell indicated by the color swap layer shape.

Abstract: According to one general aspect, a method may include dividing circuit cells into colorable sub-portions, wherein each circuit cell includes one or more colorable sub-portions. The method may include determining if a violating colorable sub-portion is to be re-colored. The method may include indicating that the violating colorable sub-portion is to be at least partially re-colored.

Abstract: According to one general aspect, a method may include receiving a data file that includes placement data regarding a plurality of circuit cells. The circuit cells may include respective layout portions. The layout portions may be associated with a plurality of respective lithographic colors. The method may include determining if a violating circuit cell is to be re-colored. The method may include indicating that, via at least one shape on a color swap layer in the data file, the violating circuit cell is to be at least partially re-colored. A color swap layer shape may cause a mask generator to re-color the portion of the violating circuit cell indicated by the color swap layer shape.

Abstract: According to one general aspect, a method may include dividing circuit cells into colorable sub-portions, wherein each circuit cell includes one or more colorable sub-portions. The method may include determining if a violating colorable sub-portion is to be re-colored. The method may include indicating that the violating colorable sub-portion is to be at least partially re-colored.

Abstract: An integrated circuit including a first circuit block having a power supply terminal for receiving a first power supply voltage and an output terminal for providing a first data signal is provided. The integrated circuit further includes a second circuit block having a power supply voltage terminal for receiving a second power supply voltage and an input terminal coupled to the output terminal of the first circuit block for receiving the first data signal. The integrated circuit further includes a first programmable delay block for adding a first delay time to the first data signal when one or both of the first or second power supply voltages is changed.

Abstract: A latch of an integrated circuit is able to retain data at the latch when the integrated circuit is in a low-power mode. The latch retains data at a retention stage in response to assertion of an isolation signal. In response to a reference voltage supplied to the latch being restored to a normal operating voltage, indicating that the integrated circuit has transitioned from the low-power mode to a normal mode, a data restoration circuit provides the retained data at the output of the latch prior to negation of the isolation signal. This reduces the likelihood that a delay in negation of the isolation signal will result in the latch output providing incorrect data, thereby reducing the likelihood of the latch output causing errors in downstream elements of the integrated circuit.

Abstract: A circuit has an input for receiving a power mode control signal to indicate a low power mode. A plurality of non-inverting buffers forms a fanout signal distribution network and provides buffering of the power mode control signal for gated power domain functional circuitry. Each non-inverting buffer has an even number of serially-connected inverting gates, at least a portion providing respective outputs having a valid logic state in the low power mode. Two voltages are used, one of which is disconnected during the low power mode. The non-inverting buffers have a first inverting gate connected to a continuous voltage terminal and a second inverting gate, collectively sized larger than the first inverting gate and connected to a voltage terminal which is selectively disconnected during the low power mode from the continuous voltage terminal.

Abstract: A circuit has an input for receiving a power mode control signal to indicate a low power mode. A plurality of non-inverting buffers forms a fanout signal distribution network and provides buffering of the power mode control signal for gated power domain functional circuitry. Each non-inverting buffer has an even number of serially-connected inverting gates, at least a portion providing respective outputs having a valid logic state in the low power mode. Two voltages are used, one of which is disconnected during the low power mode. The non-inverting buffers have a first inverting gate connected to a continuous voltage terminal and a second inverting gate, collectively sized larger than the first inverting gate and connected to a voltage terminal which is selectively disconnected during the low power mode from the continuous voltage terminal.

Abstract: A latch of an integrated circuit is able to retain data at the latch when the integrated circuit is in a low-power mode. The latch retains data at a retention stage in response to assertion of an isolation signal. In response to a reference voltage supplied to the latch being restored to a normal operating voltage, indicating that the integrated circuit has transitioned from the low-power mode to a normal mode, a data restoration circuit provides the retained data at the output of the latch prior to negation of the isolation signal. This reduces the likelihood that a delay in negation of the isolation signal will result in the latch output providing incorrect data, thereby reducing the likelihood of the latch output causing errors in downstream elements of the integrated circuit.

Abstract: An integrated circuit including a first circuit block having a power supply terminal for receiving a first power supply voltage and an output terminal for providing a first data signal is provided. The integrated circuit further includes a second circuit block having a power supply voltage terminal for receiving a second power supply voltage and an input terminal coupled to the output terminal of the first circuit block for receiving the first data signal. The integrated circuit further includes a first programmable delay block for adding a first delay time to the first data signal when one or both of the first or second power supply voltages is changed.

Abstract: A flip-flop (10) has a normal mode and a low power mode to save power. The flip-flop (10) has a master latch (14) and a slave latch (20). The slave latch (20) is used to retain the condition of the flip-flop (10) during the low power mode, where power is withdrawn from the master latch (14) but maintained on the slave latch (20). The slave latch (20) may use transistors with lower leakage characteristics than the transistors that make up the master latch (14). These lower leakage characteristics may be achieved by a higher threshold voltage and/or a thicker gate dielectric. Operating speed of the flip-flop (10) is maintained by implementing the slave latch (20) so that no logic gate or switching transistor is in the critical timing path. Instead, the slave latch (20) has an input/output terminal to tap into the signal path between the master latch and an output circuit (22).

Abstract: Methods and architectures for code phase searching spread spectrum signals having a repeating sequence of bits. The signals are searched virtually in parallel by segmenting with a divider (314) received signals by sequentially, partially correlating signal segments with a corresponding replica signal segments for a predetermined number of phase delays during a time interval not greater than that required to form the next signal segment. Multiplexors (322) and (330) provide Doppler and replica signal segments data from Doppler signal and replica signal generators (318) and (320) to corresponding multipliers (326) and (332), respectively, for multiplication with corresponding signal segments in a segment register (316). The partial correlation results for each phase delay and at each Doppler frequency are stored in corresponding memory locations in a coherent accumulation RAM (334). The signals may be searched over one or more phase delays and at one or more Doppler frequencies.

Abstract: Methods and architectures for code phase searching spread spectrum signals having a repeating sequence of bits. The signals are searched virtually in parallel by segmenting with a divider (314) received signals by sequentially, partially correlating signal segments with a corresponding replica signal segments for a predetermined number of phase delays during a time interval not greater than that required to form the next signal segment. Multiplexors (322) and (330) provide Doppler and replica signal segments data from Doppler signal and replica signal generators (318) and (320) to corresponding multipliers (326) and (332), respectively, for multiplication with corresponding signal segments in a segment register (316). The partial correlation results for each phase delay and at each Doppler frequency are stored in corresponding memory locations in a coherent accumulation RAM (334). The signals may be searched over one or more phase delays and at one or more Doppler frequencies.