Patents by Inventor Andrew P. Lyle

Andrew P. Lyle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12211571
    Abstract: Methods, systems, and devices for on-die testing for a memory device are described. In some examples, a memory die may include processing circuitry configured to perform evaluations of the memory die based on commands or instructions received from an external device. The processing circuitry may be configured to detect failures of the memory die and transmit related indications to the external device based on the on-die detection. In some examples, the processing circuitry may be configured to communicate failure information at a finer granularity than information associated with expected or nominal behavior. Additionally or alternatively, the processing circuitry may be configured to perform operations according to an internally-generated clock signal that operates at a faster rate or speed than a clock signal from the external device.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: January 28, 2025
    Assignee: Micron Technology, Inc.
    Inventors: David W. Overgaard, Andrew P. Lyle, Glen E. Hush, Timothy P. Finkbeiner, Kristopher J. Kopel, Jonathan D. Harms
  • Publication number: 20220108761
    Abstract: Methods, systems, and devices for on-die testing for a memory device are described. In some examples, a memory die may include processing circuitry configured to perform evaluations of the memory die based on commands or instructions received from an external device. The processing circuitry may be configured to detect failures of the memory die and transmit related indications to the external device based on the on-die detection. In some examples, the processing circuitry may be configured to communicate failure information at a finer granularity than information associated with expected or nominal behavior. Additionally or alternatively, the processing circuitry may be configured to perform operations according to an internally-generated clock signal that operates at a faster rate or speed than a clock signal from the external device.
    Type: Application
    Filed: October 7, 2020
    Publication date: April 7, 2022
    Inventors: David W. Overgaard, Andrew P. Lyle, Glen E. Hush, Timothy P. Finkbeiner, Kristopher J. Kopel, Jonathan D. Harms
  • Patent number: 8634233
    Abstract: Systems and methods that enable direct communications between magnetic tunnel junctions are provided. In one embodiment, a device includes multiple input magnetic tunnel junctions and an output magnetic tunnel junction. The multiple input magnetic tunnel junctions are connected in parallel, and the output magnetic tunnel junction is connected in series to the input magnetic tunnel junctions. In another embodiment, a device includes a first magnetic tunnel junction, a second magnetic tunnel junction, and a nano-magnetic channel. Each of the first and the second magnetic tunnel junctions has a free layer, a nonmagnetic layer, and a fixed layer. The nano-magnetic channel connects the free layer of the first magnetic tunnel junction to the free layer of the second magnetic tunnel junction.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: January 21, 2014
    Assignee: Regents of the University of Minnesota
    Inventors: David J. Lilja, Jian-Ping Wang, Andrew P. Lyle, Shruti R. Patil, Jonathan D. Harms, Xiaofeng Yao
  • Publication number: 20120314489
    Abstract: Systems and methods that enable direct communications between magnetic tunnel junctions are provided. In one embodiment, a device includes multiple input magnetic tunnel junctions and an output magnetic tunnel junction. The multiple input magnetic tunnel junctions are connected in parallel, and the output magnetic tunnel junction is connected in series to the input magnetic tunnel junctions. In another embodiment, a device includes a first magnetic tunnel junction, a second magnetic tunnel junction, and a nano-magnetic channel. Each of the first and the second magnetic tunnel junctions has a free layer, a nonmagnetic layer, and a fixed layer. The nano-magnetic channel connects the free layer of the first magnetic tunnel junction to the free layer of the second magnetic tunnel junction.
    Type: Application
    Filed: May 18, 2012
    Publication date: December 13, 2012
    Applicant: Regents of the University of Minnesota
    Inventors: David J. Lilja, Jian-Ping Wang, Andrew P. Lyle, Shruti R. Patil, Jonathan D. Harms, Xiaofeng Yao