Abstract: A computer implemented method for analyzing a timing of an integrated circuit, wherein an interconnection of a first net of the integrated circuit includes at least one conducting segment formed in a wiring layer or a via layer, includes obtaining a plurality of resistances and a plurality of capacitances, which correspond to each of the at least one conducting segment, based on a process variation, counting a number of layers in which the at least one conducting segments is formed, and calculating a corner resistance and a corner capacitance of the first net, based on the number of layers, the plurality of resistances, and the plurality of capacitances, wherein the counting of the number of layers includes calculating an effective number of layers based on a resistance variability and/or a capacitance variability of each of the layers.

Abstract: A semiconductor integrated circuit including a substrate, a series of metal layers, and a series of insulating layers. The metal layers and the insulating layers are alternately arranged in a stack on the substrate. The semiconductor integrated circuit also includes at least two standard cells in the substrate and at least one power rail crossing over boundaries of the at least two standard cells. The power rail includes a vertical section of conductive material extending continuously through at least two vertical levels of the stack. The two vertical levels of the stack include one metal layer and one insulating layer. The insulating layer is above the metal layer.

Abstract: According to one general aspect, an apparatus may include a metal layer having a metal pitch between metal elements, and a gate electrode layer having a gate pitch between gate electrode elements, wherein the gate electrode pitch is a ratio of the metal pitch. The apparatus may include at least two power rails coupled, by via staples, with the metal layer, wherein the via staples at least partially overlap one or more of the gate electrode elements. The apparatus may include even and odd pluralities of standard cells, each respectively located in even/odd placement sites wherein portions of the standard cells that carry signals within the metal layer do not connect to the via staples.

Abstract: According to one general aspect, an apparatus may include a metal layer having a metal pitch between metal elements, and a gate electrode layer having a gate pitch between gate electrode elements, wherein the gate electrode pitch is a ratio of the metal pitch. The apparatus may include at least two power rails coupled, by via staples, with the metal layer, wherein the via staples at least partially overlap one or more of the gate electrode elements. The apparatus may include even and odd pluralities of standard cells, each respectively located in even/odd placement sites wherein portions of the standard cells that carry signals within the metal layer do not connect to the via staples.

Abstract: According to an example embodiment, an integrated circuit may include a plurality of cells and a plurality of paths that supply power to the plurality of cells, respectively. The plurality of cells and the plurality of paths may be arranged based on a plurality of propagation delays of the plurality of cells, which include a plurality of first delays of the plurality of cells generated by a plurality of power resistances of the plurality of paths and a plurality of second delays of the plurality of cells generated based on a plurality of arrival timing windows that overlap each other.

Abstract: A computer implemented method for analyzing a timing of an integrated circuit, wherein an interconnection of a first net of the integrated circuit includes at least one conducting segment formed in a wiring layer or a via layer, includes obtaining a plurality of resistances and a plurality of capacitances, which correspond to each of the at least one conducting segment, based on a process variation, counting a number of layers in which the at least one conducting segments is formed, and calculating a corner resistance and a corner capacitance of the first net, based on the number of layers, the plurality of resistances, and the plurality of capacitances, wherein the counting of the number of layers includes calculating an effective number of layers based on a resistance variability and/or a capacitance variability of each of the layers.

Abstract: A method of analyzing an integrated circuit, which is implemented by a computing system or a processor, wherein an interconnection of a first net of the integrated circuit includes at least one conducting segment corresponding to one wiring layer or one via, includes receiving a plurality of resistances and a plurality of capacitances, which correspond to the first net, based on a process variation, counting a number of conducting segments corresponding to the first net, and calculating a first resistance or a first capacitance of the first net, based on the number of conducting segments, the plurality of resistances, and the plurality of capacitances.

Abstract: According to an example embodiment, an integrated circuit may include a plurality of cells and a plurality of paths that supply power to the plurality of cells, respectively. The plurality of cells and the plurality of paths may be arranged based on a plurality of propagation delays of the plurality of cells, which include a plurality of first delays of the plurality of cells generated by a plurality of power resistances of the plurality of paths and a plurality of second delays of the plurality of cells generated based on a plurality of arrival timing windows that overlap each other.

Abstract: A semiconductor integrated circuit including a substrate, a series of metal layers, and a series of insulating layers. The metal layers and the insulating layers are alternately arranged in a stack on the substrate. The semiconductor integrated circuit also includes at least two standard cells in the substrate and at least one power rail crossing over boundaries of the at least two standard cells. The power rail includes a vertical section of conductive material extending continuously through at least two vertical levels of the stack. The two vertical levels of the stack include one metal layer and one insulating layer. The insulating layer is above the metal layer.

Abstract: According to one general aspect, a method may include receiving a circuit model that includes logic circuits that are represented by respective cells. The method may include providing a timing adjustment to the circuit model. This providing may include determining one or more respective cells that are candidates for adjustment by employing a sub-micron stress effect, and, for each candidate, replacing a candidate cell with a stressed cell, wherein a candidate cell and stressed cell perform a same logical function. Each stressed cell may include: a gate electrode, a first gate-cut shape disposed to cut the gate electrode, wherein the first gate-cut shape is disposed upon a row-boundary, a second gate-cut shape disposed upon the row-boundary, a gate-cut break disposed between the first gate-cut shape and the second gate-cut shape, an active region, and an active-cut shape disposed to cut the active region.

Abstract: According to one general aspect, a method may include receiving a circuit model that includes logic circuits that are represented by respective cells. The method may include providing a timing adjustment to the circuit model. This providing may include determining one or more respective cells that are candidates for adjustment by employing a sub-micron stress effect, and, for each candidate, replacing a candidate cell with a stressed cell, wherein a candidate cell and stressed cell perform a same logical function. Each stressed cell may include: a gate electrode, a first gate-cut shape disposed to cut the gate electrode, wherein the first gate-cut shape is disposed upon a row-boundary, a second gate-cut shape disposed upon the row-boundary, a gate-cut break disposed between the first gate-cut shape and the second gate-cut shape, an active region, and an active-cut shape disposed to cut the active region.

Abstract: A method of analyzing an integrated circuit, which is implemented by a computing system or a processor, wherein an interconnection of a first net of the integrated circuit includes at least one conducting segment corresponding to one wiring layer or one via, includes receiving a plurality of resistances and a plurality of capacitances, which correspond to the first net, based on a process variation, counting a number of conducting segments corresponding to the first net, and calculating a first resistance or a first capacitance of the first net, based on the number of conducting segments, the plurality of resistances, and the plurality of capacitances.

Abstract: A method for forming al buried contact begins by forming an exposed contact area (22) of a substrate (10) having a surface (11). An undoped or lightly doped layer of polysilicon (32) is formed in contact with the contact area (22). A contiguous masking layer (36) is formed over one or more of the contact areas (22) to cover a contact portion of the layer (32) while exposing other portions of the layer (32). The other portions of the layer (32) are doped with dopant atoms (44). A heat cycle is used to laterally drive the dopant atoms (44) through the layer (32) and downward through a substrate surface (11) to form buried contact substrate-diffused regions (54). The resulting regions (54) have improved voltage punch-through resistance to laterally adjacent electrical diffusion regions since the masking layer (36) creates a longer thermal diffusion path for the dopant atoms which eventually reside in the regions (54).